3.16.4. Status Register, ETMSR

The ETMSR characteristics are:

Purpose

Provides information about the current status of the trace and trigger logic.

Usage constraints

This is a Read/Write register with some bits that are Read Only.

Configurations

Available in all PTM implementations.

Attributes

See the register summary in Table 3.16.

Figure 3.15 shows the ETMSR bit assignments.

Figure 3.15. ETMSR bit assignments

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Table 3.20 shows the ETMSR bit assignments.

Table 3.20. ETMSR bit assignments

Bits

Type

Description

[31:4]-Reserved, SBZP.
[3]RW

Trigger bit.

Set when the trigger occurs, and prevents the trigger from being output until the PTM is next programmed. For more information see Programming bit and associated state.

[2]

RW

Holds the current status of the trace start/stop resource. If set to 1, it indicates that a trace start address has been matched, without a corresponding trace stop address match.

[1]

RO

Indicates the current effective value of ProgBit, bit [10] of the ETMCR. You must wait for this bit to go to 1 before you start to program the PTM. See Programming bit and associated state.

If you read other bits in the ETMSR while this bit is 0, some instructions might not have taken effect. ARM recommends that you set the Programming bit to 1 and then wait for this bit to go to 1 before interpreting any other values in this register or reading any other register.

This bit remains 0 while there is any data in the FIFO. This ensures that the FIFO is empty before you can reprogram the PTM.

Note

From PFT v1.1, this bit is set when OS Lock is also set.

[0]

RO

If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0 when either:

  • trace is restarted

  • the PTM Power Down bit, bit [0] of the Main Control Register, 0x000, is set to 1.

Note

Setting or clearing the Programming bit, ProgBit, does not clear this bit to 0.


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