3.2.2. Topology detection requirements

A PTM must implement the logical interfaces that Table 3.1 lists. Each logical interface must implement registers to support topology detection. See the CoreSight Architecture Specification.

Table 3.1. Required PTM logical interfaces

Trace outputMaster1
ProcessorSlave1 + (value of bits [14:12] of ETMSCR
External outputMasterValue of bits [22:20] of ETMCCR
External inputSlaveValue of bits [19:17] of ETMCCR
Trigger outputMaster1

For more information about the registers referred to in Table 3.1, see:

In any CoreSight component, registers 0x380-0x3BF are reserved for topology detection and integration registers, and use of these registers for this purpose is implementation defined.

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