3.9. PTM counters

A PTM can include one or more counters, that you control using PTM events, and configure using the counter registers. For a PTM implementation, the number of counters is implementation defined. A PTM implementation:

Each implemented counter is controlled by two events, and has two other associated registers:

The counter enable event

While the counter enable event is TRUE, the counter is enabled and counts down.

Each counter is 16-bit, so it can count from 1 to 65535. While a counter is enabled, it is clocked by the system clock, even on cycles when the processor is stalled, and decrements on each clock cycle.

Use the Counter Enable Event Register to define the event that enables the counter. See Counter Enable Event Registers, ETMCNTENRn.

The counter reload event

If the counter reload event occurs, the counter is reloaded from the Counter Reload Value Register. See Counter Reload Value Registers, ETMCNTRLDVRn.

The counter reload event takes priority over the counter enable event.

Use the Counter Reload Event Register to define the event that causes a counter reload. See Counter Reload Event Registers, ETMCNTRLDEVRn.

The Counter Reload Value Register

This register holds the value that is loaded into the counter when the Counter Reload Event is TRUE. See Counter Reload Value Registers, ETMCNTRLDVRn.

The Counter Value Register

You can:

  • read this register at any time to find the current value of the counter

  • write a new value to this register when you are programming the PTM.

For more information see Counter Value Registers, ETMCNTVRn.

When a counter reaches zero it remains at zero and the associated resource becomes active, and remains active until the counter is reloaded.

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