CoreSight Program Flow Trace Architecture SpecificationPFTv1.0 and PFTv1.1
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3.16.28. ID Register, ETMIDR

The ETMIDR characteristics are:

Purpose

  • Holds the PTM architecture variant.

  • Defines the programmers model for the PTM.

Usage constraints

There are no usage constraints.

Configurations

Available in all PTM implementations.

Attributes

See the register summary in Table 3.16.

Figure 3.35 shows the ETMIDR bit assignments.

Figure 3.35. ETMIDR bit assignments

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Table 3.44 shows the ETMIDR bit assignments.

Table 3.44. ETMIDR bit assignments

BitsDescription
[31:24]

Implementer code. The following codes are defined[a], and all other values are reserved by ARM Limited:

0x41

ASCII code for A, indicating ARM Limited.

0x44

ASCII code for D, indicating Digital Equipment Corporation.

0x4D

ASCII code for M, indicating Motorola, Freescale Semiconductor Inc.

0x51

ASCII code for Q, indicating QUALCOMM Inc.

0x56

ASCII code for V, indicating Marvell Semiconductor Inc.

0x69

ASCII code for i, indicating Intel Corporation.

[23:21]Reserved, RAZ.
[20]Reserved, This bit is RAO.
[19]

Support for Security Extensions. The possible values of this bit are:

0

The PTM behaves as if the processor is in Secure state at all times.

1

The ARM architecture Security Extensions are implemented by the processor.

[18]

Support for 32-bit Thumb instructions. The possible values of this bit are:

0

A 32-bit Thumb instruction is traced as two instructions, and exceptions might occur between these two instructions.

1

A 32-bit Thumb instruction is traced as a single instruction.

See 32-bit Thumb instructions for more information.

[17:16]Reserved, RAZ.
[15:12]Reserved. This field reads as b1111.
[11:8]Major architecture version number. See Product revision status. A value of b0011 is used for PFTv1.
[7:4]

Minor architecture version number. See Product revision status. The possible values for this field are:

b0000 = PFTv1.0

b0001 = PFTv1.1.

All other values are Reserved.

[3:0]Implementation revision. This matches the Revision field in the Peripheral ID2 register. See Peripheral ID2 Register, ETMPIDR2.

[a] The Implementer code list applies to all ARM processor and trace architectures. This list does not indicate the implementer of PFT architectures.


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