3.22.1. PTM state definitions, PFTv1.1 with multiple power implementations

The following list shows the definitions of PTM states for multiple power implementations, from PFTv1.1. These states determine the behavior of accesses to the registers listed in the tables in this section.

No Debug Power

This behavior applies when the debug domain is powered down. Also, for memory-mapped accesses, this behavior applies when DBGSWENABLE is LOW.

No Core Power

The behavior applies when all of the following apply:

  • the core power domain is powered down.

  • for debugger and memory-mapped accesses, the PTM is not in the No Debug Power state

OS Lock set

The behavior applies when all of the following apply:

  • the PTM is not in the No Debug Power state

  • the PTM is not in the No Core Power state

  • the OS Lock is set to 1.

Non-Privileged

This behavior applies to coprocessor accesses when all of the following apply:

  • the PTM is not in the No Debug Power state

  • the PTM is not in the No Core Power state

  • the processor is operation in a Non-Privileged mode

  • accesses to the trace unit are disabled using the CPACR, NSACR, or HCPTR.

This state takes precedence over the OS Lock Set state.

If the PTM is in a state which is not covered by one of these definitions then the general access permissions apply as defined in the Otherwise column in each table.

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