3.16.59. Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR7

The characteristics for ETMPIDR5 to ETMPIDR7 are:


Reserved for future expansion of the CoreSight peripheral identification information.

Usage constraints

From PFTv1.1, accesses to these registers from the coprocessor interface are unpredictable.


These registers are defined as reserved registers.


See the register summary in Table 3.16.

Figure 3.64 shows the ETMPIDR5 to ETMPIDR7 bit assignments.

Figure 3.64. ETMPIDR5 to ETMPIDR7 bit assignments

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Table 3.75 shows the ETMPIDR5 to ETMPIDR7 bit assignments.

Table 3.75. ETMPIDR5 to ETMPIDR7 bit assignments


Table 3.68 shows the register addresses and memory offsets for these registers.

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