3.16.16. Counter Enable Event Registers, ETMCNTENRn

The ETMCNTENR characteristics are:



  • defines the event that enables the corresponding counter

  • can be used to configure the counter for continuous operation.

Usage constraints

Each ETMCNTENR is used with a corresponding ETMCNTRLDVR, ETMCNTRLDEVR, and ETMCNTVR. See About the counter registers.


The number of ETMCNTENRs:

  • is implementation defined

  • is specified by ETMCCR bits [15:13]

  • can be zero.

See Configuration Code Register, ETMCCR.

Unimplemented ETMCNTENRs are RAZ/WI.


See the register summary in Table 3.16.

Figure 3.25 shows the ETMCNTENR bit assignments.

Figure 3.25. ETMCNTENR bit assignments

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Table 3.32 shows the ETMCNTENR bit assignments.

Table 3.32. ETMCNTENR bit assignments



[31:18]Reserved, SBZP.


Reserved, RAO/WI.


This bit is RAO/WI for consistency with previous ARM trace architectures.


Count enable event. Subdivided as:

Function, bits [16:14]

Specifies the logical operation that combines the two resources that define the event.

Resource B, bits [13:7] and Resource A, bits [6:0]

Specify the two resources that are combined by the logical operation specified by the Function field.

For more information see Event resources and PTM events.

To configure a continuous counter, program the function field as b000, to select Resource A, and the Resource A field to select the always TRUE resource. See The PTM event resources.

Each of the Counter Enable Event Registers has the same bit assignments.

Defining a PTM event describes how you define a counter enable event.

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