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| Home > Program Trace Macrocell Programmers Model > PTM register descriptions > Counter Enable Event Registers, ETMCNTENRn | |||
The ETMCNTENR characteristics are:
An ETMCNTENR:
defines the event that enables the corresponding counter
can be used to configure the counter for continuous operation.
Each ETMCNTENR is used with a corresponding ETMCNTRLDVR, ETMCNTRLDEVR, and ETMCNTVR. See About the counter registers.
The number of ETMCNTENRs:
is implementation defined
is specified by ETMCCR bits [15:13]
can be zero.
See Configuration Code Register, ETMCCR.
Unimplemented ETMCNTENRs are RAZ/WI.
See the register summary in Table 3.16.
Figure 3.25 shows the ETMCNTENR bit assignments.
Table 3.32 shows the ETMCNTENR bit assignments.
Table 3.32. ETMCNTENR bit assignments
Bits | Description |
|---|---|
| [31:18] | Reserved, SBZP. |
[17] | Reserved, RAO/WI. NoteThis bit is RAO/WI for consistency with previous ARM trace architectures. |
[16:0] | Count enable event. Subdivided as:
For more information see Event resources and PTM events. To configure a continuous counter, program the function field as b000, to select Resource A, and the Resource A field to select the always TRUE resource. See The PTM event resources. |
Each of the Counter Enable Event Registers has the same bit assignments.
Defining a PTM event describes how you define a counter enable event.