3.16.19. About the sequencer registers

A PTM implementation can include a sequencer. If it does, software controls the sequencer by defining the events that cause the sequencer to move between its different states.

Each sequencer state transition event has its own register, and these registers are programed to control the state transitions. An additional register holds the current state of the sequencer. Table 3.35 lists the sequencer registers, with the register number and address offset of each register.

When programming the sequencer, you must program a valid encoding into each ETMSQabEVR, otherwise the behavior of the sequencer is unpredictable. For example, if you want the sequencer only to perform transitions between states 1 and 2, you must:

If the sequencer must be in a particular state when the Programming bit is cleared, the Sequencer State Register (0x067) should be written after programming the Sequencer State Transition Event Registers to ensure this value is used. If the Sequencer State Register is not written then the sequencer state resets to 1 when the ETM Programming bit is cleared.

Programming any of the Sequencer State Transition Event Registers when the Programming bit is set to 1 resets the sequencer to State 1. This behavior is implementation defined.

Table 3.35. Sequencer register allocation

Register

Short name

Description

NumberOffset [a]

0x060

0x180

ETMSQ12EVR

State 1 to State 2 Transition Event Register [b]

0x061

0x184

ETMSQ21EVR

State 2 to State 1 Transition Event Register [b]

0x062

0x188

ETMSQ23EVR

State 2 to State 3 Transition Event Register [b]

0x063

0x18C

ETMSQ31EVR

State 3 to State 1 Transition Event Register [b]

0x064

0x190

ETMSQ32EVR

State 3 to State 2 Transition Event Register [b]

0x065

0x194

ETMSQ13EVR

State 1 to State 3 Transition Event Register [b]

0x066

0x198

-

Reserved

0x067

0x19C

ETMSQR

Current Sequencer State Register. See Current Sequencer State Register, ETMSQR

[a] Register offset where the registers are accessed in a memory-mapped scheme. The register offset is always 4 × (Register number).

[b] Each of the Sequencer State Transition Event Registers has the same bit assignments. See Sequencer State Transition Event Registers, ETMSQabEVR for details.


Copyright © 1999-2002, 2004-2008, 2011 ARM. All rights reserved.ARM IHI 0035B
Non-ConfidentialID060811