3.16.1. Main Control Register, ETMCR

The ETMCR characteristics are:

Purpose

Controls general operation of the PTM, such as whether tracing is enabled or is cycle-accurate.

Usage Constraints

There are no usage constraints.

Configurations

Available in all PTM implementations.

Attributes

See the register summary in Table 3.16.

Figure 3.12 shows the ETMCR bit assignments for PFTv1.1.

Figure 3.12. ETMCR bit assignments

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Table 3.17 shows the ETMCR bit assignments.

Table 3.17. ETMCR bit assignments

Bits

Name

Function

[31]

Reserved

SBZP.
[30]Reserved

For PFTv1.0 this bit is Reserved, SBZP.

VMID trace enable

For PFTv1.1:

  • This bit controls VMID tracing. Set this bit to 1 to enable VMID tracing. See Virtualization.

  • If bit [26] of the Configuration Code Extension Register is zero, indicating that Virtualization support is not implemented, this bit is RAZ/WI.

  • A PTM reset sets this bit to 0.

[29]Return stack enable

Set this bit to 1 to enable use of the return stack. See Use of a return stack.

You must not set this bit to 1 if bit [8] of this register is set to 1 to enable branch broadcasting . Behavior is unpredictable if you enable both use of the return stack and branch broadcasting.

If bit [23] of the Configuration Code Extension Register is zero, indicating that the return stack is not implemented, this bit is RAZ/WI.

A PTM reset sets this bit to 0.

[28]Timestamp enable

Set this bit to 1 to enable timestamping. See Timestamping.

If bit [22] of the Configuration Code Extension Register is zero, indicating that timestamping is not implemented, this bit is RAZ/WI.

A PTM reset sets this bit to 0.

[27:25]

Processor select

If a PTM is shared between multiple processors, selects the processor to trace. For the maximum value permitted, see bits [14:12] of ETMSCR. See Table 3.21.

To guarantee that the PTM is correctly synchronized to the new processor, you must update these bits as follows:

  1. Set bit [10], Programming bit, to b1.

  2. Poll bit [1] of the Status Register until it is set to b1, as described in Use of the Programming bit.

  3. Set bit [0], PowerDown, to b1.

  4. Change the Processor select bits.

  5. Clear bit [0], PowerDown, to b0.

  6. Perform other programming required as normal.

You must not set this field to a value greater than bits [14:12] of the System Configuration Register.

On a PTM reset these bits are all zero.

[24]Instrumentation resources access control

When this bit is set to 1, the Instrumentation resources can only be controlled when the processor is in a privileged mode.

When this bit is set to 0, the Instrumentation resources can be accessed in both privileged and User modes.

If no Instrumentation resources are implemented this bit is RAZ/WI. Bits [15:13] of the Configuration Code Extension Register indicate the number of implemented Instrumentation resources.

A PTM reset sets this bit to 0.

[23:16]

Reserved

SBZP.

[15:14]

ContextIDsize

The possible values of this field are:

b00

No Context ID tracing.

b01

One byte traced, Context ID bits [7:0].

b10

Two bytes traced, Context ID bits [15:0].

b11

Four bytes traced, Context ID bits [31:0].

Note

The PTM traces only the number of bytes specified, even if the new Context ID value is larger than this.

If Context ID tracing is not supported these bits are RAZ/WI.

A PTM reset sets these bits to zero.

[13]

Reserved

SBZP.

[12]

CycleAccurate

Set this bit to 1 to enable cycle-accurate tracing. See Cycle-accurate tracing.

If the implementation does not support cycle-accurate tracing this bit is RAZ/WI.

A PTM reset sets this bit to 0.

[11]

Reserved

SBZP.

[10]

ProgBit

Programming bit. You must set this bit to 1 to program the PTM, and clear it to 0 when programming is complete. See Programming bit and associated state.

A PTM reset sets this bit to 1.

[9]

Debug request control[a]

When this bit is set to 1 and the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables a debugger to force the ARM processor into Debug state.

A PTM reset sets this bit to 0.

Note

If the Programming Bit or the OS Lock are set before the processor has entered debug state, it is implementation defined whether the PTM sustains this request. The processor might or might not enter debug state.

[8]

BranchBroadcast

Set this bit to 1 to enable branch broadcasting. Branch broadcasting traces the addresses of direct branch instructions. See Branch broadcasting.

You must not set this bit to 1 if bit [29] of this register is set to 1 to enable use of the return stack. Behavior is unpredictable if you enable both use of the return stack and branch broadcasting.

If the implementation does not support branch broadcasting this bit is RAZ/WI.

A PTM reset sets this bit to 0.

[7]

Stall processor

Set this bit to 1 to enable the use of the FIFOFULL output to stall the processor to prevent overflow:

  • when this bit is 0, FIFOFULL remains LOW at all times and the FIFO overflows if there are too many trace packets

  • when this bit is 1, FIFOFULL is asserted when the trace FIFO is nearly full, and can be used to stall the processor.

See FIFOFULL Level Register, ETMFFLR for more information.

If the FIFOFULL signal is not implemented then this bit is RAZ/WI.

A PTM reset sets this bit to 0.

[6:1]

Reserved

SBZP.

[0]

PowerDown

A pin controlled by this bit enables the PTM power to be controlled externally. The external pin is often PTMPWRDOWN, or inverted as PTMPWRUP. This bit must be cleared by the trace software tools at the beginning of a debug session.

When this bit is set to 1, the PTM must be powered down and disabled, and then operated in a low power mode with all clocks stopped.

When this bit is set to 1, writes to some registers and fields might be ignored. You can always write to the following registers and fields:

  • ETMCR, bit [0] and bits [27:25]

  • ETMLAR

  • ETMCLAIMSET

  • ETMCLAIMCLR

  • ETMOSLAR.

When ETMCR is written with this bit set to 1, writes to bits other than bits [27:25, 0] might be ignored.

A PTM reset sets this bit to 1.

[a] When this bit is set, the PTM requests the processor to enter debug state when a PTM trigger occurs. If the Programming Bit or the OS Lock are set before the processor has entered debug state, it is implementation defined whether the PTM sustains this request. The processor might or might not enter debug state.


Checking support for implementation defined features

The values of ETMCR bits specify whether the PTM supports the following implementation defined features:

  • VMID tracing, controlled by bit [30]

  • the return stack, controlled by bit [29]

  • timestamping, controlled by bit [28]

  • Context ID tracing, controlled by bits [15:14]

  • cycle-accurate tracing, controlled by bit [12]

  • branch broadcasting, controlled by bit [8]

  • FIFOFULL stalling, controlled by bit [7].

You can read the System Configuration Register, the Configuration Code Register, and the Configuration Code Extension Register to determine whether some of these features are supported. However, if a feature is not supported then its control field in the Main Control Register is RAZ/WI. Therefore, debug tools can perform a sequence of read, modify, write, and re-read on the Main Control Register to find the features that are supported. To avoid changing other PTM control settings, the test process is:

  1. Ensure that, in the ETMCR, the Programming bit, bit [10], is set to 1, and the PowerDown bit, bit [0], is set to 0.

  2. Read the ETMCR, and save a copy of the returned value.

  3. Modify the returned data, setting bits [29:28,15:14,12,8,7] to 1.

  4. Write the modified value back to the ETMCR.

  5. Read the ETMCR again, and check each of bits [29:28,15:14,12,8,7] to see whether the feature is supported. For fields other than the ContextIDsize field, the meaning of the value returned is:

    bit == 0

    feature not supported

    bit == 1

    feature is supported.

    For the ContextIDsize field, bits [15:14], the meaning of the value returned is:

    bits [15:14] == 0

    Context ID tracing not supported

    bits [15:14] > 0

    Context ID tracing is supported.

  6. Write the value from step 2 back to the ETMCR to restore its original value.

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