3.16.53. About the Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all CoreSight components. They are a set of eight registers, listed in register number order in Table 3.68:

Table 3.68. Summary of the peripheral identification registers

RegisterDescriptionNumberOffset [a]
Peripheral ID4See Peripheral ID4 Register, ETMPIDR40x3F40xFD0
Peripheral ID5See Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR70x3F50xFD4
Peripheral ID60x3F60xFD8
Peripheral ID70x3F70xFDC
Peripheral ID0See Peripheral ID0 Register, ETMPIDR00x3F80xFE0
Peripheral ID1See Peripheral ID1 Register, ETMPIDR10x3F90xFE4
Peripheral ID2See Peripheral ID2 Register, ETMPIDR20x3FA0xFE8
Peripheral ID3See Peripheral ID3 Register, ETMPIDR30x3FB0xFEC

[a] Register offset where the registers are accessed in a memory-mapped scheme. The register offset is always 4 × (Register number).


Only bits [7:0] of each Peripheral ID Register are used, with bits [31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID, as Figure 3.57 shows.

Figure 3.57. Mapping between the Peripheral ID Registers and the Peripheral ID value

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Figure 3.58 shows the standard Peripheral ID fields in the single conceptual Peripheral ID.

Figure 3.58. Peripheral ID fields for an ARM implementation

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Table 3.69 shows the standard Peripheral ID fields, and shows where this information is held in the Peripheral ID Registers.

Table 3.69. Register fields for the Peripheral ID registers

NameSizeDescriptionSee Register
4KB Count4 bitsLog2 of the number of 4KB blocks occupied by the device. PTM implementations occupy a single 4KB block, so this field is always 0x0.Peripheral ID4
JEP 106 code4+7 bitsIdentifies the designer of the device. This consists of a 4-bit continuation code and a 7-bit identity code. For a PTM designed by ARM the continuation code is 0x4 and the identity code is 0x3B, indicating ARM.Peripheral ID1, Peripheral ID2, Peripheral ID4
Part Number12 bitsPart number for the device.Peripheral ID0, Peripheral ID1
Revision4 bitsRevision of the peripheral. Peripheral ID2
RevAnd4 bitsIndicates a late modification to the device, usually as a result of an Engineering Change Order.Peripheral ID3
Customer modified4 bitsIndicates an endorsed modification to the device.Peripheral ID3

For more information about these fields, see the CoreSight Architecture Specification.

In PFTv1.0, the revision field in the ETMIDR and ETMPIDR2 are identical. In PFTv1.1:

ARM recommends that implementations keep these values identical to ensure revision numbers can be managed easily. However, in cases where an ECO fix is required and changing both revisions is difficult, it is acceptable to change the revision fields independently. The next official implementation should re-align the revision numbers, potentially missing values from either field.

The following sections describe the fields present in each register. Registers are described in register name order, ID0 to ID7. Table 3.68 shows the register numbers and offset addresses of these registers, that do not run in register name order.

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