3.3.1. About TraceEnable

Figure 3.1 shows the TraceEnable components and the logical connections between them. The final TraceEnable signal is asserted to enable tracing, and deasserted to disable tracing.

Figure 3.1. The TraceEnable mechanism

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Figure 3.1 shows that three controls are required to activate TraceEnable:

The TraceEnable enabling event

The PTM recognizes a number of resources, that you can use to define PTM events. See Event resources and PTM events. You must program the TraceEnable Event Register to define the event that enables TraceEnable activation.

The TraceEnable start/stop block

The TraceEnable start/stop block has separate start and stop controls. The inputs to each control are:

  • selected single address comparators (SACs)

  • selected Embedded ICE watchpoints, from the processor.

When an input to the start control is activated, the block turns on and asserts its output.

When an input to the stop control is activated, the block turns off and deasserts its output, if necessary.

The Trace start/stop control enable bit in the TraceEnable Control Register controls whether the output of the TraceEnable start/stop block must be asserted for TraceEnable to be asserted. However, the output of the start/stop block is always available as a PTM resource, regardless of the state of the Trace start/stop control enable bit.

You program the:

  • TraceEnable Start/Stop Control Register to define the SACs that trigger the start control, and the SACs that trigger the stop control

  • TraceEnable Start/Stop EmbeddedICE Control Register to define the EmbeddedICE watchpoints that trigger the start control, and the EmbeddedICE watchpoints that trigger the stop control.

For more information about the TraceEnable Start/Stop block see The TraceEnable start/stop block.

Address range comparators

You use address range comparators (ARCs) to define either the code regions that are included in the PTM trace, or the code regions that are excluded from the trace. The Include/exclude bit in the TraceEnable Control Register controls whether the ARCs are used to include code regions, or to exclude code regions.

For information about the address comparators, including how they are used to define ARCs, see Address comparators. For more information about how ARCs are used by the TraceEnable mechanism to include or exclude regions of code from the PTM trace see TraceEnable Include/exclude control.

This means that the PTM generates trace when all the following conditions are met:

Figure 3.2 summarizes how you program the TraceEnable logic.

Figure 3.2. Programming the TraceEnable logic

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


For descriptions of the registers used to program TraceEnable, see:

Imprecise TraceEnable events

If TraceEnable is imprecise for any reason, any of the following might occur:

  • tracing might not turn on in time to trace the required instruction

  • tracing might not turn off in time to avoid tracing a specific instruction

  • trace might be missing at the start of a trace region

  • extra trace might appear at the end of a trace region.

Except for some implementation defined configurations, the TraceEnable signal is imprecise only if the resource that causes it to change is one of the following:

  • a resource that is selected by the enabling event

  • an address comparator linked to a Context ID comparator, and the Context ID changes.

See the appropriate PTM Technical Reference Manual for details of any implementation defined configurations for which the TraceEnable signal is not imprecise.

Copyright © 1999-2002, 2004-2008, 2011 ARM. All rights reserved.ARM IHI 0035B
Non-ConfidentialID060811