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| Home > Program Trace Macrocell Programmers Model > Access permissions for PFTv1.0 with multiple power implementations > PTM state definitions, PFTv1.0 with multiple power implementations | |||
The following list shows the definitions of PTM states for multiple power implementations in PFTv1.0. These states determine the behavior of accesses to the registers listed in the tables in this section.
This behavior applies if the PTM is powered down. Also, for memory-mapped accesses, this state applies when DBGSWENABLE is LOW.
This behavior applies when all the following apply:
the PTM is not in the No Debug Power state
the core domain is powered down.
This behavior applies when all the following apply:
the PTM is not in the No Debug Power state
the PTM is not in the No Core Power state
the Sticky State is set to 1.
This behavior applies when all the following apply:
the PTM is not in the No Debug Power state
the PTM is not in the No Core Power state
the PTM is not in the Sticky State Set state
the OS Lock is set to 1.
This behavior applies to coprocessor accesses when all the following apply:
the PTM is not in the No Debug Power state
the PTM is not in the No Core Power state
the processor is operating in a Non-Privileged mode
accesses to the trace unit are disabled using the CPACR, NSACR, or HCPTR.
This state takes precedence over the Sticky State Set or OS Lock Set states.
If the PTM is in a state which is not covered by one of these definitions then the general access permissions apply as defined in the Otherwise column in each table.
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