3.16.10. FIFOFULL Level Register, ETMFFLR

The ETMFFLR characteristics are:

Purpose

Defines the level below which the FIFO is considered full.

Usage constraints

There are no usage constraints.

Configurations

Available in all PTM implementations.

Attributes

See the register summary in Table 3.16.

Figure 3.20 shows the ETMFFLR bit assignments.

Figure 3.20. ETMFFLR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.25 shows the ETMFFLR bit assignments.

Table 3.25. ETMFFLR bit assignments

Bits

Description

[31:8]Reserved.
[7:0]

The number of bytes left in the FIFO, below which the FIFOFULL signal is asserted. For example, setting this value to 15 causes processor stalling, if enabled, when there are less than 15 free bytes in the FIFO.


The maximum valid value for this register is the size of the FIFO. This causes FIFOFULL to be asserted whenever the FIFO is not empty. Behavior is unpredictable if the value 0 is written to this register and Stall processor is selected in the Main Control Register, 0x000.

If a value larger than the FIFO size is written to the ETMFFLR, the FIFO size itself is selected, and is the value returned when the register is read.

You can use FIFOFULL control only if it is supported by both the PTM and the processor it is connected to:

You can use FIFOFULL control only when both these bits are set to 1.

If the PTM does not implement processor stalling, this register is reserved, and you cannot use the programmers model to determine the FIFO size. If a PTM does not implement processor stalling, bit [23] of the ETMCCR is RAZ. See Configuration Code Register, ETMCCR.

Copyright © 1999-2002, 2004-2008, 2011 ARM. All rights reserved.ARM IHI 0035B
Non-ConfidentialID060811