3.15.6. Organization of the PTM registers

Table 3.16 lists the PTM registers, in register order. In the table, access type is described as follows:

RW

Read and write

RO

Read only

WO

Write only.

Table 3.16. PTM registers summary

Register [a]

Name

Type

Description

0x000-0x0BF, Trace registers [b]
 

0x000

Main Control

RW

See Main Control Register, ETMCR

 

0x001

Configuration Code

RO

See Configuration Code Register, ETMCCR

 

0x002

Trigger Event

RW

See Trigger Event Register, ETMTRIGGER

 

0x003

Reserved-

-

 

0x004

Status

RW

See Status Register, ETMSR

 

0x005

System Configuration

RO

See System Configuration Register, ETMSCR

 

TraceEnable configuration. See About the TraceEnable control registers:

 0x006

TraceEnable Start/Stop Control

RW

See TraceEnable Start/Stop Control Register, ETMTSSCR

 

0x007

Reserved-

-

 

0x008

TraceEnable Event

RW

See TraceEnable Event Register, ETMTEEVR

 

0x009

TraceEnable Control

RW

See TraceEnable Control Register, ETMTECR1

 

0x00A

Reserved-

-

 

FIFOFULL configuration:

 

0x00B

FIFOFULL Level

RW

See FIFOFULL Level Register, ETMFFLR

 

0x00C-0x00F

Reserved-

-

 

Address comparators. See About the address comparator registers:

 

0x010- 0x01F

Address Comparator Value 1-16

RW

See Address Comparator Value Registers, ETMACVRn

 

0x020- 0x02F

Address Comparator Access Type 1-16

RW

See Address Comparator Access Type Registers, ETMACTRn

 0x030- 0x04FReserved-

-

 

Counters. See About the counter registers:

 

0x050-0x053

Counter Reload Value 1-4

RW

See Counter Reload Value Registers, ETMCNTRLDVRn

 

0x054-0x057

Counter Enable Event 1-4

RW

See Counter Enable Event Registers, ETMCNTENRn

 

0x058-0x05B

Counter Reload Event 1-4

RW

See Counter Reload Event Registers, ETMCNTRLDEVRn

 

0x05C-0x05F

Counter Value 1-4

RW

See Counter Value Registers, ETMCNTVRn

 

Sequencer. See About the sequencer registers:

 

0x060-0x065

Sequencer State Transition Event 1-6

RW

See Sequencer State Transition Event Registers, ETMSQabEVR

 

0x066

--Reserved
 

0x067

Current Sequencer State

RW

See Current Sequencer State Register, ETMSQR

 External output event:
 

0x068-0x06B

External Output Event 1-4

RW

See External Output Event Registers, ETMEXTOUTEVRn

 

Context ID comparators. See About the Context ID comparator registers:

 

0x06C-0x06E

Context ID Comparator Value

RW

See Context ID Comparator Value Registers, ETMCIDCVRn

 

0x06F

Context ID Comparator Mask

RW

See Context ID Comparator Mask Register, ETMCIDCMR

 Other trace [b] registers:
 

0x070-0x077

Implementation specificRW

See Implementation specific registers, ETMIMPSPEC0 to ETMIMPSPEC7

 

0x078

Synchronization Frequency

RW

See Synchronization Frequency Register, ETMSYNCFR

 

0x079

ID

RO

See ID Register, ETMIDR

 

0x07A

Configuration Code ExtensionRO

See Configuration Code Extension Register, ETMCCER

 0x07BExtended External Input SelectionRW

See Extended External Input Selection Register, ETMEXTINSELR

 0x07CTraceEnable Start/Stop EmbeddedICE Control

RW

See TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR

 0x07DEmbedded ICE Behavior Control

RW

See EmbeddedICE Behavior Control Register, ETMEIBCR

 

0x07E

Timestamp EventRW

See Timestamp Event Register, ETMTSEVR

 

0x07F

Auxiliary ControlRW

See Auxiliary Control Register, ETMAUXCR

 0x080CoreSight Trace IDRW

See CoreSight Trace ID Register, ETMTRACEIDR

 0x081-0x08F--Reserved
 0x090VMID Comparator Value RegisterRWSee VMID Comparator Value Register, ETMVMIDCVR
 

0x091-0x0BF

--Reserved
0x0C0-0x0C5, Management registers [b]
 Operating system save and restore registers. See About the Operating System Save and Restore registers:
 0x0C0OS Lock AccessWO

See OS Lock Access Register, ETMOSLAR

 0x0C1OS Lock StatusRO

See OS Lock Status Register, ETMOSLSR

 0x0C2OS Save/RestoreRW

See OS Save and Restore Register, ETMOSSRR

 Other management registers:
 

0x0C3-0x0C3

--Reserved
 0x0C4Power-Down ControlRWSee Device Power-Down Control Register, ETMPDCR
 0x0C5Power-Down StatusRW

See Device Power-Down Status Register, ETMPDSR

0x0C6-0x3BF, Trace registers [b]
 

0x0C6-0x37F

--Reserved
 0x380-0x3BFIntegration registers-Reserved for implementation defined topology detection and integration test registers
0x3C0-0x3FF, Management registers [b]
 

0x3C0

Integration Mode ControlRW

See Integration Mode Control Register, ETMITCTRL

 0x3E8Claim Tag SetRW

See Claim Tag Set Register, ETMCLAIMSET

 0x3E9Claim Tag ClearRW

See Claim Tag Clear Register, ETMCLAIMCLR

 0x3ECLock AccessWO

See Lock Access Register, ETMLAR

 0x3EDLock StatusRO

See Lock Status Register, ETMLSR

 0x3EEAuthentication StatusRO

See Authentication Status Register, ETMAUTHSTATUS

 0x3F2Device ConfigurationRO

See Device Configuration Register, ETMDEVID

 0x3F3Device TypeRO

See Device Type Register, ETMDEVTYPE

 Peripheral and Component ID registers:
 0x3F4Peripheral ID4RO

See Peripheral ID4 Register, ETMPIDR4

 0x3F5Peripheral ID5RO

Reserved in current implementations. See Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR7

 0x3F6Peripheral ID6RO
 0x3F7Peripheral ID7RO
 0x3F8Peripheral ID0RO

See Peripheral ID0 Register, ETMPIDR0

 0x3F9Peripheral ID1RO

See Peripheral ID1 Register, ETMPIDR1

 0x3FAPeripheral ID2RO

See Peripheral ID2 Register, ETMPIDR2

 0x3FBPeripheral ID3RO

See Peripheral ID3 Register, ETMPIDR3

 0x3FCComponent ID0RO

See Component ID0 Register, ETMCIDR0

 0x3FDComponent ID1ROSee Component ID1 Register, ETMCIDR1
 0x3FEComponent ID2ROSee Component ID2 Register, ETMCIDR2
 0x3FFComponent ID3ROSee Component ID3 Register, ETMCIDR3

[a] The Register column gives the register number. Registers are numbered sequentially from zero. Where registers are accessed in a memory-mapped scheme, the offset of a register is (4 × register number).

[b] For more information about the division into Trace and Management registers, see PTM trace and PTM management registers.


For details of the access controls on the PTM registers see About the access permissions for PTM registers.

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