3.16.32. EmbeddedICE Behavior Control Register, ETMEIBCR

The ETMEIBCR characteristics are:

Purpose

Controls the sampling behavior of the EmbeddedICE watchpoint comparator inputs.

Usage constraints

There are no usage constraints.

Configurations

This is an optional register. Bit [21] of the ETMCCER is set to 1 if the ETMEIBCR is implemented. See Configuration Code Extension Register, ETMCCER.

Attributes

See the register summary in Table 3.16.

Figure 3.39 shows the ETMEIBCR bit assignments.

Figure 3.39. ETMEIBCR bit assignments

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Table 3.48 shows the ETMEIBCR bit assignments.

Table 3.48. ETMEIBCR bit assignments

Bits

Description

[31:8]Reserved, SBZP.

[7:0]

EmbeddedICE watchpoint comparator input sampling behavior. Each bit controls the sampling behavior of one of the EmbeddedICE watchpoint comparator inputs:

Bit == 0

When sampled, the corresponding input is pulsed for a single sample.

Bit == 1

When sampled, the corresponding input is latched and held until one cycle before the next sampling point.

Bit [0] corresponds to input 1, bit [1] to input 2, and this pattern continues up to bit [7] corresponding to input 8.


For more information about the behavior of the EmbeddedICE watchpoint comparator inputs see EmbeddedICE watchpoint comparator input behavior.

Note

If the EmbeddedICE Behavior Control Register is not implemented, the EmbeddedICE watchpoint comparator inputs must behave as described in Default behavior of EmbeddedICE watchpoint comparator inputs.

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