3.16.31. TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR

The ETMTESSEICR characteristics are:

Purpose

Specifies the EmbeddedICE watchpoint comparator inputs that are used as trace start and stop resources.

Usage constraints

There are no usage constraints.

Configurations

Available in all PTM implementations.

The number of EmbeddedICE watchpoint comparators:

  • is implementation defined

  • is specified by ETMCCER bits [19:16]

  • can be zero.

See Configuration Code Extension Register, ETMCCER.

If the PTM does not implement any EmbeddedICE watchpoint comparators then the ETMTESSEICR is RAZ/WI.

Attributes

See the register summary in Table 3.16.

Figure 3.38 shows the ETMTESSEICR bit assignments.

Figure 3.38. ETMTESSEICR bit assignments

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Table 3.47 shows the ETMTESSEICR bit assignments.

Table 3.47. ETMTESSEICR bit assignments

Bits

Description

[31:24]Reserved, SBZP.

[23:16]

TraceEnable stop control selection. Setting a bit in this field to 1 selects the corresponding EmbeddedICE watchpoint comparator input as a TraceEnable stop control, for the Start/Stop block. Bit [16] corresponds to input 1, bit [17] to input 2, and this pattern continues up to bit [23] corresponding to input 8.

[15:8]Reserved, SBZP.

[7:0]

TraceEnable start control selection. Setting a bit in this field to 1 selects the corresponding EmbeddedICE watchpoint comparator input as a TraceEnable start control, for the Start/Stop block. Bit [0] corresponds to input 1, bit [1] to input 2, and this pattern continues up to bit [7] corresponding to input 8.


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