3.17.2. Power down support from PFTv1.1

Two levels of power down support are provided in PFTv1.1, SinglePower and Full support.

SinglePower from PFTv1.1

A SinglePower implementation can be identified by reading the ETMOSLSR. If bit [3] and bit [0] of the ETMOSLSR are both 0 then this is a SinglePower implementation.

SinglePower implementations do not support tracing over a power down. To avoid losing PTM state when the processor is powered down, one of the following options must be used:

  • Do not power down the processor. This can be achieved by setting the DBGNOPWRDWN bit in the processor debug registers.

  • The PTM must remain powered when the processor is powered down. This involves implementing the PTM in a separate power domain from the processor.

  • The PTM registers must be manually saved by software running on the processor. This mechanism does not guarantee that the processor and an external debugger will not conflict while the saving and restoring is taking place.

A SinglePower implementation has the following attributes:

  • The OS Lock is not implemented:

    • The ETMOSLAR is not implemented and ignores writes

    • The ETMOSSRR is not implemented and accesses to the ETMOSSRR are unpredictable

    • The ETMOSLSR always reads as 0x00000000.

  • The ETMPDSR always reads as 0x00000001.

For more details on Access permissions in SinglePower implementations see Access permissions for PFTv1.1 SinglePower implementations .

Full Power Down Support from PFTv1.1

An implementation with Full Power Down support can be identified by reading the ETMOSLSR. If bit [3] is 1 and bit [0] is 0 then the implementation has full power down support.

Full power down support from PFTv1.1 has the following attributes:

  • The OS Lock is implemented:

    • The OS Lock is set from a PTM reset.

    • The ETMOSLAR is implemented.

    • The ETMOSSRR is not implemented. Trace registers must be manually saved and restored while the OS Lock is set.

    • When the OS Lock is set, accesses to Trace registers from an external debugger return an Error.

  • The ETMPDSR is fully implemented:

    • The StickyState bit has no effect on accesses to any registers.

For more details on Access permissions implementations with full power down support see Access permissions for PFTv1.1 with multiple power implementations.

To save the PTM trace registers, perform the following steps:

  1. If you are using a memory-mapped interface, unlock the CoreSight Lock, if implemented. See About the lock registers.

  2. Set the OS Lock using the ETMOSLAR. See About the Operating System Save and Restore registers.

  3. Poll ETMSR bit [1] until it becomes set, indicating the PTM is idle. See Status Register, ETMSR.

  4. Manually read the PTM trace registers and save the contents to memory.

  5. The PTM core domain can now be powered down.

If the procedure is terminated early, for example if the power down sequence is terminated before this procedure is complete, if the OS Lock is cleared before the ETMSR bit [1] is set then the PTM might not restart tracing immediately and the PTM resources might not become active immediately.

To restore the PTM trace registers, perform the following steps:

  1. If you are using a memory-mapped interface, unlock the CoreSight Lock, if implemented. See About the lock registers.

  2. The OS Lock must be set from an PTM reset. Check this by reading the ETMOSLSR. See OS Lock Status Register, ETMOSLSR.

  3. Poll the ETMSR bit [1] until it becomes set, indicating the PTM is idle. See Status Register, ETMSR.

  4. Manually restore the PTM trace registers from memory.

  5. Clear the OS Lock using the ETMOSLAR. See OS Lock Access Register, ETMOSLAR.

Significant changes to power down support introduced in PFTv1.1

  • The ETMOSSRR is never implemented.

  • If implemented, the OS Lock is set from a PTM reset.

  • If implemented, if the OS Lock is set it only causes an error response to debugger accesses to the PTM Trace registers.

  • If implemented, the ETMPDSR bit [1], Sticky Register State, no longer has any effect on accesses to any PTM registers.

  • The OS Lock status is visible in the ETMPDSR.

  • The Claim tag registers are now PTM Trace registers and must be saved and restored manually.

  • The ETMSR bit [1] becomes set when the PTM becomes idle after setting the OS Lock. This is used to indicate that the PTM is sufficiently idle for the PTM trace registers to be saved or restored.

  • Access permissions to some registers are changed. See About the access permissions for PTM registers

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