3.17.1. Power down support in PFTv1.0

Two levels of power down support are provided in PFTv1.0, SinglePower and Full support.

SinglePower in PFTv1.0

A SinglePower implementation can be identified by reading the ETMOSLSR. If bit [3] and bit [0] of the ETMOSLSR are both 0 then this is a SinglePower implementation.

SinglePower implementations do not support tracing over a power down. To avoid losing PTM state when the processor is powered down, one of the following options must be used:

  • Do not power down the processor. This can be achieved by setting the DBGNOPWRDWN bit in the processor debug registers.

  • The PTM must remain powered when the processor is powered down. This involves implementing the PTM in a separate power domain from the processor.

  • The PTM registers must be manually saved by software running on the processor. This mechanism does not guarantee that the processor and an external debugger will not conflict while the saving and restoring is taking place.

A SinglePower implementation has the following attributes:

  • The OS Lock is not implemented:

    • The ETMOSLAR is not implemented and ignores writes

    • The ETMOSSRR is not implemented and accesses to the ETMOSSRR are Unpredictable

    • The ETMOSLSR always reads as 0x00000000

  • The ETMPDSR always reads as 0x00000001.

For more details on Access permissions in SinglePower implementations see Access permissions for PFTv1.0 SinglePower implementations.

Full Power Down Support in PFTv1.0

An implementation with Full Power Down support can be identified by reading the ETMOSLSR. If bit [3] is b0 and bit [0] is b1 then the implementation has full power down support.

Full power down support has the following attributes:

  • The OS Lock is implemented:

    • The ETMOSLAR is implemented

    • The ETMOSSRR is implemented and is used to save and restore the PTM trace registers

    • When the OS Lock is set, accesses to Trace registers return an Error.

  • The ETMPDSR is fully implemented:

    • When the StickyState bit [1] is set, accesses to Trace registers return an Error.

For more details on Access permissions implementations with full power down support see Access permissions for PFTv1.0 with multiple power implementations.

To save the PTM trace registers, perform the following steps:

  1. If you are using a memory-mapped interface, unlock the CoreSight Lock, if implemented. See About the lock registers.

  2. Read the ETMPDSR to clear the StickyState bit if it is set. See Device Power-Down Status Register, ETMPDSR.

  3. Set the OS Lock using the ETMOSLAR. See About the Operating System Save and Restore registers.

  4. Use the ETMOSSRR to read out the ETM registers and save them to memory. See OS Save and Restore Register, ETMOSSRR.

  5. The PTM core domain can now be powered down.

To restore the PTM trace registers, perform the following steps:

  1. If you are using a memory-mapped interface, unlock the CoreSight Lock, if implemented. See About the lock registers.

  2. Read the ETMPDSR to clear the StickyState bit. See Device Power-Down Status Register, ETMPDSR.

  3. Set the OS Lock if it is not already set using the ETMOSLAR. See About the Operating System Save and Restore registers.

  4. Use the ETMOSSRR to restore the ETM registers from memory. See OS Save and Restore Register, ETMOSSRR.

  5. Clear the OS Lock using the ETMOSLAR. See OS Save and Restore Register, ETMOSSRR.

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