3.16.14. About the counter registers

There are between zero and four 16-bit counters. Four registers are used to define the operation of each counter. The following sections describe the counter registers:

Table 3.30 summarizes the Counter registers:

Table 3.30. Summary of Counter registers

CounterCounter Registers:
Reload Value [a]Enable [a] Reload Event [a]Value [a]
10x0500x0540x0580x05C
20x0510x0550x0590x05D
30x0520x0560x05A0x05E
40x0530x0570x05B0x05F

[a] Register numbers are listed. Where registers are accessed in a memory-mapped scheme, the register offset is 4 × (Register number).


See PTM counters for more information about the counter registers.

Reduced function counter, from PFTv1.1

From PFTv1.1, counter 1 can be implemented as a counter with reduced functionality. The reduced function counter has the following attributes:

  • 16-bit reload value, configured by ETMCNTRLDVR1.

  • Decrements on every cycle. ETMCNTENR1 is Reserved.

  • Reloads every time the counter reaches zero. ETMCNTRLDEVR1 is Reserved.

  • The counter value cannot be read. ETMCNTVR1 is Reserved.

  • The counter always starts at the reload value when the PTM programming bit is cleared.

  • The value cannot be saved or restored.

Bit [27] of the ETMCCER identifies whether counter 1 is a reduced function counter. See Configuration Code Extension Register, ETMCCER.

If more than 1 counter is implemented, the counters other than counter 1 are always full function counters.

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