3.19.1. PTM state definitions, PFTv1.0 SinglePower implementations

The following list shows the definitions of PTM states for SinglePower implementations in PFTv1.0. These states determine the behavior of accesses to the registers listed in the tables in this section.

No Power

This behavior applies if the PTM is powered down. Also, for memory-mapped accesses, this state applies when DBGSWENABLE is LOW.


This behavior applies to coprocessor accesses when all of the following apply:

  • the PTM is not in the No Power state

  • the processor is operating in a Non-Privileged mode

  • accesses to the trace unit are disabled using the CPACR, NSACR, or HCPTR.

If the PTM is in a state which is not covered by one of these definitions then the general access permissions apply as defined in the Otherwise column in each table.

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