4.5.2. I-sync, instruction synchronization packet

Periodically, the PTM outputs an I-sync packet. This packet consists of:

Figure 4.2 shows the structure of the I-sync packet from PFTv1.1.

Figure 4.2. I-sync instruction synchronization packet, PFTv1.1

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


An I-sync packet comprises the following contiguous components:

I-sync header

Indicates that this is an I-sync packet.

Address

The address depends on why the packet was generated, as indicated by the Reason field. Normally, the address indicated for each reason code is:

Periodic

Most recent waypoint target address, or last nonperiodic I-sync address if there has not been a waypoint since the last nonperiodic I-sync packet.

Trace_on

Most recent waypoint target address or exception target address.

Overflow

Most recent waypoint target address or exception target address.

Debug

Address of the first instruction out of Debug state.

T

Indicates the processor instruction set state when the instruction at the address specified by the Address field is executed. The possible values are:

0

ARM state.

1

Thumb state, or ThumbEE state. See the AltIS bit for more information.

Information byte

In this byte:

  • Bits [6:5] indicate the reason why this I-sync packet was generated. The possible values are:

    00, Periodic

    Periodic I-sync.

    01, Trace_on

    Trace turned on normally.

    10, Overflow

    FIFO overflow.

    11, Debug

    Exit from Debug state.

    For more information see Periodic and Nonperiodic I-sync packets.

  • Bit [3] is set to 1 if the processor is in Non-secure state at the address specified in the Address field.

  • Bit [2], when the T bit is set to 1, indicates the processor instruction set state when the instruction at the address specified by the Address field is executed. The possible values are:

    0

    Thumb state.

    1

    ThumbEE state.

    When the T bit is set to 0, this bit is Reserved, SBZ.

  • Bit [1]:

    • For PFTv1.0, this bit is Reserved, SBZ.

    • For PFTv1.1, in implementations that include the Virtualization extension, this bit is set to 1 if the processor is in Hyp mode.

Cycle count
Context ID

The current Context ID. This is the Context ID of the instruction at the address specified by the Address field.

An I-sync packet does not indicate that the instruction at the address given in the packet was executed. You must look at the subsequent packets to determine whether that instruction was executed.

On return from Jazelle state, the Address field gives the address of the first instruction out of Jazelle state.

On return from a region where tracing is prohibited, the Address field gives the address of the first instruction that is not in the prohibited region.

For more information about instruction synchronization see Instruction synchronization.

The I-sync cycle count field

In the first I-sync packet after the PTM is enabled, the cycle count packet indicates the number of cycles since the Programming bit was cleared to 0.

The cycle count is always the incremental cycle count up to the last waypoint, not up to the time the I-sync packet was generated. After the first I-sync packet, the I-sync cycle count field indicates the number of cycles from the last cycle count to the time of the waypoint instruction indicated in the address field of the packet. Table 4.2 shows an example of the cycle count values output during tracing.

Table 4.2. Cycle count example with late trace turn-on

CycleExecutionTrace and countCount
0Waypoint ATraced-
10Waypoint BTraced, count=10 (10-0)10 (10-0)
30Waypoint C

Indicator that execution reached Waypoint C, count=20 (30-10). Trace turned off here.

20 (30-10)
50Waypoint D--
60-Trace turned on here. I-sync for Waypoint D.20 (50-30) [a]
70Waypoint ETraced20 (70-50) [b]
100Waypoint FTraced30 (100-70)

[a] The cycle count is the number of cycles between the last cycle count, cycle 30, and the last waypoint, Waypoint D. It does not indicate where tracing was turned on.

[b] The cycle count is the number of cycles since the last cycle count. That is, the number of cycles between Waypoint D and Waypoint E.


From PFTv1.1, the cycle count value in an I-Sync packet which indicates a Trace Overflow or Debug Exit is unknown and must not be relied on.

Periodic and Nonperiodic I-sync packets

The reason code of a periodic I-sync packet is b00. No cycle count bytes are output in a periodic I-sync packet.

A nonperiodic I-sync packet is an I-sync packet with a reason code other than b00. If cycle-accurate mode is enabled, a nonperiodic I-sync packet always includes one or more cycle count bytes. The cycle count is compressed. See Cycle count compression. The final cycle count byte output cannot be zero.

When a nonperiodic I-sync packet is generated, its reason code is determined by applying the following rules, in order:

  1. If Halting debug-mode is enabled and the I-sync packet indicates the first nonprohibited instruction since exit from Debug state, then the reason code is b11, exit from Debug state.

  2. If the PTM has recovered from a FIFO overflow, the reason code is b10, FIFO overflow.

  3. Otherwise, the reason code is b01, Trace turned on normally.

The priority of these rules means that the FIFO overflow reason code is lost if both of the following apply:

  • Halting debug-mode is enabled and the overflow occurred immediately before entry to Debug state

  • you trace the first instruction after exit from Debug state.

Copyright © 1999-2002, 2004-2008, 2011 ARM. All rights reserved.ARM IHI 0035B
Non-ConfidentialID060811