CoreSight Program Flow Trace Architecture Specification: 4.5.10. Exception return packet

4.5.10. Exception return packet

A PTM for an ARMv7 processor generates an exception return packet to indicate that the processor is returning from an exception handler. ARMv7-M code performs an exception return by moving a special value to the PC. A debugger cannot determine this return from the program image. However, any instruction that modifies the PC is a waypoint instruction, and therefore an exception return packet in the trace stream indicates that the most recent waypoint instruction was the exception return instruction.

Table 4.11 shows the instructions that generate an exception return.

Table 4.11. Exception return instructions

Description	Example Mnemonic	ARM Profile
Load multiple with the PC and CPSR	`LDM` (exception return)	ARMv-7A, ARMv7-R, ARMv6 and earlier
Return from Exception	`RFE`
Data processing instruction that modifies the PC and has the S bit set	`MOVS PC, LR PC, SUBS PC, LR`
Exception return^[a]	`ERET`
POP or LDM that loads into the PC	`LDM, POP`	ARMv7-M^[b]
Load to the PC	`LDR PC`
Branch and exchange with any register	`BX Rn`
^[a]Only if the Virtualization Extensions are implemented. SeeVirtualization. ^[b]In ARMv7-M, these instructions are only considered to be exception return instructions if they transfer one of the special values into the PC.

The exception return packet is always one byte, and consists of the exception return header. See Figure 4.44.

Figure 4.44. Exception return packet

This packet is only generated for ARMv7-A, ARMv7-R, and ARMv6 processors when PFTv1.1 is implemented. It is not generated for ARMv7-A, ARMv7-R, and ARMv6 processors if PFTv1.0 is implemented.

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