4.5.4. Branch address packet

The PTM generates a branch address packet to indicate a change in the program flow. It outputs a branch address packet when any of the following occurs:

The branch address packet generated when an exception occurs is called an exception branch address packet, and is indicated by a nonzero Exception field. Branch address packets are sometimes called branch packets.

A non-exception branch address packet implies an E atom before the branch.

A branch address packet consists of 1-5 address bytes followed by 0-2 exception information bytes. The exact format of the packet depends on the instruction set state of the processor after the branch is taken:

As Table 4.1 shows, the first address byte of the packet is also recognized as the packet header.

In cycle-accurate mode, the branch address packet is extended by 1-5 bytes of cycle count. See Branch address packet cycle count information in cycle-accurate mode.

Figure 4.5. Full branch address packet with exception, ARM state

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Figure 4.6. Full branch address packet with exception, Thumb state

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Figure 4.7. Full branch address packet with exception, Jazelle state

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The fields in the branch address packet are:

Address

The target address, 1-5 bytes. The PTM compresses the address section of a branch address packet, by generating only the bytes required to output all the address bits that are changed, compared with the address in the last branch address packet or I-sync packet. However, the address section is not compressed when the instruction alignment changes, for example from ARM to Thumb. See Address and cycle count compression in branch address packets for more information.

Exception information

0-2 bytes of additional information, that indicate:

  • the exception that occurred, if any

  • the NS value

  • the AltIS value, if the branch address packet indicates a change to or from ThumbEE state.

The PTM generates Exception information byte 0 only if at least one of the following applies:

  • The value of the AltIS bit has changed since the last branch address packet or I-sync packet. This applies if the processor changes instruction set state to or from ThumbEE state.

  • The value of the NS bit has changed since the last branch address packet or I-sync packet. This applies if the processor changes security state.

  • An exception caused the change in program flow.

The PTM generates Exception information byte 1 only if the exception causing the change in program flow has an exception number greater than 15 (greater than b1111).

From PFTv1.1, for implementations that support virtualization, bit [5] of information byte 1 is set to 1 when the processor operates in Hyp mode.

Exception[3:0]

If the branch address packet includes at least one exception information byte, Table 4.4 lists the meaning of the Exception[3:0] field.

Table 4.4. Values of Exception[3:0] for ARMv7-A and ARMv7-R processors

Exception[3:0]Exception
b0000None
b0001Entered Debug state when Halting debug-mode is enabled
b0010Secure Monitor Call (SMC)
b0011PFTv1.0: Reserved
From PFTv1.1: entry to Hyp mode
b0100Asynchronous Data Abort
b0101ThumbEE check failed
b011xReserved
b1000Processor Reset
b1001Undefined Instruction
b1010Supervisor Call (SVC)
b1011Prefetch Abort or software breakpoint
b1100Synchronous Data Abort or software watchpoint
b1101Generic exception
b1110IRQ
b1111FIQ

NS

If the branch address packet includes at least one exception information byte, NS is set to 1 if the processor is in Non-secure state when the instruction at the address specified by the Address field is executed, and otherwise is set to 0.

AltIS

If a branch address packet includes at least one exception information byte, the AltIS bit indicates the processor instruction set state when the instruction at the address specified by the Address field is executed. The possible values are:

0

Thumb state.

1

ThumbEE state.

In ARM and Jazelle state branch address packets this bit is always 0.

Hyp

If a branch address packet includes two exception information bytes, the Hyp bit indicates if the processor is branching into Hyp mode. The possible values are:

0

Processor is not branching into Hyp mode.

1

Processor is branching into Hyp mode.

The Hyp field is only set to 1 from PFTv1.1 and when the Virtualization extensions are implemented.

The branch address packet does not include any exception information bytes if all of the following apply:

Note

  • The PTM does not support tracing in Jazelle state, but it traces any branch into Jazelle state, using the Jazelle state format in Figure 4.7.

  • A non-exception branch address packet implies an E atom.

Branch address packet cycle count information in cycle-accurate mode

If you enable cycle-accurate tracing, by setting bit [12] of the Main Control Register to 1, each branch address packet is followed immediately with 1-5 bytes of cycle count information. Figure 4.8 shows the format of the cycle count bytes.

Figure 4.8. Branch address packet cycle count bytes, when cycle-accurate tracing is enabled

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The PTM compresses the branch address packet cycle count information, by not generating any leading bytes that are zero. This compression is described as leading-zero compression. See Address and cycle count compression in branch address packets for more information.

A cycle count of all 1s, corresponding to the value 0xFFFF FFFF, indicates a cycle count overflow. This means that the valid cycle count range is 0 to (231 - 2), 0x0000 0000 to 0xFFFF FFFE.

Note

The format of the cycle count field permits a cycle count of 0, because a processor might execute two branches in the same cycle. In this case, if you have enabled cycle-accurate tracing, the branch address packet of the second branch includes a cycle count of 0.

Address and cycle count compression in branch address packets

When generating branch address packets, the PTM compresses the address and cycle count sections of the packet, generating the minimum possible number of bytes:

  • for the cycle count, the PTM does not generate any leading bytes that would be zero

  • for the address, the PTM does not generate any leading bytes that have not changed since the last branch address or I-sync packet.

However, the address section is not compressed when the instruction address alignment changes, for example from ARM to Thumb. This is because address byte 4 indicates the instruction address alignment. See Figure 4.5, Figure 4.6, and Figure 4.7.

The following subsections give more information about the compression, with examples of the different lengths of the address and cycle count packet sections:

Address compression

When generating branch address packets, the PTM compresses the address, generating only the bytes required to output the address bits that have changed since the last branch address or I-sync packet. So, for example, if the most significant address bit that changes is bit [11], the PTM generates only two address bytes. Figure 4.9 shows this address compression example, for a Thumb state packet that does not require any exception information bytes.

Figure 4.9. Address bytes when bit [11] is the most significant bit that changes, in Thumb state

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Note

All of the generated address bits are always valid. So, in Figure 4.9, the bits marked c are output with the correct values even though their values have not changed since the last branch address or I-sync packet.

Table 4.5 shows how the number of address bytes generated depends on:

  • The most significant bit (MSB) of the address that changes, compared with the address in the last branch address or I-sync packet.

  • The instruction set state of the processor after the branch. This determines the format of the branch address packet. See Figure 4.5 to Figure 4.7.

  • In some cases, whether the PTM must include an information byte in the packet.

Table 4.5. Number of address bytes generated for branch address packets

MSB of address that changes [a], for given stateInformation byte required?Number of address bytes generated
ARM stateThumb state
7 to 26 to 1No1
7 to 26 to 1Yes2
13 to 812 to 7-2
20 to 1419 to 13-3
27 to 2126 to 20-4
31 to 2831 to 27-5

[a] Most significant bit (MSB) of address that changes, compared with the address in the last branch address or I-sync packet.


Note

  • A PTM traces entry into Jazelle state, but does not trace instruction execution in Jazelle state, and therefore there is no requirement for address compression in Jazelle state.

  • The entry into Jazelle state is always traced with five address bytes, because of the change in instruction address alignment.

In all branch address packets, regardless of whether the PTM compresses the address:

  • in all address bytes, bit [7] is 0 if this is the last address byte in the packet, and is 1 if another address byte follows

  • in address bytes 1-4, if bit [7] is zero, bit [6] indicates whether at least one exception information byte follows the address byte.

Note

When the PTM must generate one or more exception information bytes it must generate at least two address bytes.

Table 4.6 shows how to interpret bit [7] of address byte 0, and Table 4.7 shows how to interpret bits [7:6] of address bytes 1-4. These tables apply regardless of whether the PTM has performed address compression.

Table 4.6. Interpretation of bit [7] in address byte 0

Address byte 0, bit [7]Interpretation
1The address continues in the next byte of the packet
0This is the only address byte in the packet, and there are no exception information bytes [a]

[a] If you have enabled cycle-accurate tracing at least one cycle count byte follows this byte.


Table 4.7. Interpretation of bits [7:6] in the address bytes 1-4

Address bytes 1-4Interpretation
Bit [7]Bit [6]
1-The address continues in the next byte of the packet. Bit [6] of this byte is part of the address field.
01This is the final address byte of this packet. There is at least one exception information byte after this byte.
00This is the final address byte of this packet, and there are no exception information bytes. [a]

[a] If you have enabled cycle-accurate tracing at least one cycle count byte follows this byte.


The following subsections show all the possible branch address packet formats with address compression:

Branches to Thumb or ThumbEE state, without exception information byte

The following figures show all possible packet formats for branches to Thumb or ThumbEE state that do not require an exception information byte. If there is a change of instruction address alignment that does not require an exception information byte then the PTM generates the five-bye packet in Figure 4.14. This happens when there is a change from ARM or Jazelle state to Thumb state.

Note

The figure titles refer only to Thumb state, but each figure applies to branches to both Thumb state and ThumbEE state.

Figure 4.10. Branch to Thumb state with change in A[6:1], no exception information byte

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Figure 4.11. Branch to Thumb state with change in A[12:7], no exception information byte

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Figure 4.12. Branch to Thumb state with change in A[19:13], no exception information byte

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Figure 4.13. Branch to Thumb state with change in A[26:20], no exception information byte

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Figure 4.14. Branch to Thumb state with change in A[31:27], no exception information byte

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Branches to Thumb or ThumbEE state, with exception information byte

The following figures show all possible packet formats for branches to Thumb or ThumbEE state that require an exception information byte. If a packet requires an exception information byte the PTM must generate at least two address bytes.

Note

  • The figure titles refer only to Thumb state, but each figure applies to branches to both Thumb state and ThumbEE state.

  • Most of the figures in this subsection show only a single exception information byte. However, the PFT architecture permits two exception information bytes. Figure 4.16 shows this format.

Figure 4.15. Branch to Thumb state with change in A[12:1], with exception information byte

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Figure 4.16. Branch to Thumb state with change in A[12:1], with two exception information bytes

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Figure 4.17. Branch to Thumb state with change in A[19:13], with exception information byte

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Figure 4.18. Branch to Thumb state with change in A[26:20], with exception information byte

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Figure 4.19. Branch to Thumb state with change in A[31:27], with exception information byte

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Branches to ARM state, without exception information byte

The following figures show all possible packet formats for branches to ARM state that do not require an exception information byte. If there is a change of instruction address alignment that does not require an exception information byte then the PTM generates the five-bye packet in Figure 4.24. This happens when there is a change from Thumb or Jazelle state to ARM state.

Figure 4.20. Branch to ARM state with change in A[7:2], no exception information byte

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Figure 4.21. Branch to ARM state with change in A[13:8], no exception information byte

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Figure 4.22. Branch to ARM state with change in A[20:14], no exception information byte

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Figure 4.23. Branch to ARM state with change in A[27:21], no exception information byte

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Figure 4.24. Branch to ARM state with change in A[31:28], no exception information byte

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Branches to ARM state, with exception information byte

Figure 4.25 to Figure 4.28 show all possible packet formats for branches to ARM state that require an exception information byte. If a packet requires an exception information byte the PTM must generate at least two address bytes.

Note

The figures in this subsection show only a single exception information byte. However, the PFT architecture permits two exception information bytes, and this format is shown, for a branch to Thumb state, in Figure 4.16.

Figure 4.25. Branch to ARM state with change in A[13:2], with exception information byte

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Figure 4.26. Branch to ARM state with change in A[20:14], with exception information byte

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Figure 4.27. Branch to ARM state with change in A[27:21], with exception information byte

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Figure 4.28. Branch to ARM state with change in A[31:28], with exception information byte

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Cycle count compression

The PTM generates the minimum number of cycle count bytes required to hold the cycle count value. For example, if the most significant (MS) nonzero bit of the cycle count is bit [13], the PTM generates only three cycle count bytes, as Figure 4.29 shows.

Figure 4.29. Cycle count bytes when bit [13] is the MS nonzero bit

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Table 4.8 shows how, when cycle-accurate tracing is enabled, the number of cycle count bytes generated depends on the MS nonzero bit of the cycle count.

Table 4.8. Number cycle count bytes generated for branch address packets

MS nonzero bit of cycle countNumber of cycle count bytes generated
3 to 01
10 to 42
17 to 113
24 to 184
31 to 255

The following diagrams show each of these cases, for the cycle count bytes in an address packet:

  • Figure 4.30 shows the single cycle count byte generated when the MS nonzero bit is in the range Count[3:0]

  • Figure 4.31 shows the two cycle count bytes generated when the MS nonzero bit is in the range Count[10:4]

  • Figure 4.32 shows the three cycle count bytes generated when the MS nonzero bit is in the range Count[17:11]

  • Figure 4.33 shows the four cycle count bytes generated when the MS nonzero bit is in the range Count[24:18]

  • Figure 4.34 shows the five cycle count bytes generated when the MS nonzero bit is in the range Count[31:25].

Figure 4.30. Cycle count byte when MS nonzero bit is in Count[3:0]

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Figure 4.31. Cycle count bytes when MS nonzero bit is in Count[10:4]

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Figure 4.32. Cycle count bytes when MS nonzero bit is in Count[17:11]

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Figure 4.33. Cycle count bytes when MS nonzero bit is in Count[24:18]

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Figure 4.34. Cycle count bytes when MS nonzero bit is in Count[31:25]

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