1.1.6. Resets

This document refers to the following resets and reset operations:

Processor reset

This resets the processor, making it start execution from the reset vector address. It does not reset any PTM registers. The PTM indicates the processor reset by inserting an exception packet in the trace stream. The exception packet indicates that the exception was a processor reset.

PTM reset

This is the main reset for the entire PTM, and resets all resettable PTM registers. The PTM register descriptions in PTM register descriptions define the registers that can be reset.

Power-on reset

Whether a PTM supports a power-on reset is implementation defined. If power-on reset is supported, a power-on reset must perform a PTM reset.

Writing to the Programming bit

Writing to the Programming bit of the Main Control Register is a reset operation that resets parts of the PTM to their PTM reset state. You reset some parts of the PTM by writing a 1 to this bit, and reset other parts by writing 0 to this bit. For more information see Programming bit and associated state.

On a PTM reset, the state of the Main Control Register is reset to the state described in Table 3.17. In particular, the Power-down bit and the Programming bit are set to 1.

On a PTM reset, the status of registers or individual bits is unknown if not specified in the register description.


See Programming bit and associated state for details of how the value of the Programming bit affects the register reset values on a PTM reset.

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