5.2.3. Exception occurs immediately after another exception

If two exceptions occur back-to-back, without the processor executing any instructions between them, then the PTM traces each exception with an exception branch address packet, without any waypoint update packet between them. In the trace stream, an exception branch address packet occurring immediately after another exception branch address packet indicates that one exception occurred immediately after the other.

For example, consider the case where an FIQ interrupts an IRQ:

The FIQ handler returns to the IRQ handler as if it was a normal branch. Therefore, for execution up to the entry to the FIQ handler, the PTM must generate a trace stream that indicates that both exceptions occurred, without any instructions being executed at the IRQ vector address. Table 5.3 shows how this is traced.

Table 5.3. Tracing back-to-back exceptions

AddressInstructionTrace, if any, with explanation
0x1000MOVNonwaypoint instruction. Not traced when processor executes the instruction.
-IRQ occurs

The PTM upgrades the MOV at 0x1000 to a waypoint instruction and generates a waypoint update packet with address 0x1000 [a]. It then issues an exception branch address packet, indicating an IRQ, with a destination address of 0x0018, the IRQ vector address .

-FIQ occurs

No instruction executed at 0x0018. To trace the FIQ, the PTM issues an exception branch address packet, indicating an FIQ, with a destination address of 0x001C, the FIQ vector address .

The last instruction executed is the upgraded waypoint instruction at 0x1000.

0x001CLDR PC, loads 0x2000Traced as a normal indirect branch, with a branch address packet with a destination address of 0x2000.
0x2000(FIQ handler)Traced normally. Depending on the instruction stream and TraceEnable configuration, the PTM might generate some packets.
-
-
-
0x2100SUBS PC, R14, #4Return from FIQ handler, returns to IRQ vector. PTM traces the return with a non-exception branch address packet with a destination address of 0x0018.
0x3000(IRQ handler)Traced normally. Depending on the instruction stream and TraceEnable configuration, the PTM might generate some packets.
-
-
-
0x3100SUBS PC, R14, #4Return from IRQ handler, returns to instruction after the last executed instruction. PTM traces the return with a non-exception branch address packet with a destination address of 0x1004.
0x1004MOV-

[a] If the PTM is holding any assembled atoms it outputs these atoms in an atom header before generating the waypoint update packet. This means that the trace output stream has any outstanding atoms, followed by the waypoint update packet, followed by the exception branch address packet.


When the PTM detects that two exceptions have occurred back-to-back:

Note

A processor microarchitecture might not permit two exceptions to behave in the way shown in Table 5.3.

Exceptions occurring close together but not back-to-back

For comparison with the tracing of back-to-back exceptions, this subsection gives examples of the PTM trace generated when the FIQ occurs after the processor has executed the instruction at the IRQ vector.

In the first example, the processor executes a branch at the IRQ vector address before the FIQ occurs. Table 5.4 shows this case.

Table 5.4. Normal tracing of an FIQ after executing a branch at the IRQ vector address

AddressInstructionTrace, if any, with explanation
0x1000MOVNonwaypoint instruction. Not traced when processor executes the instruction.
-IRQ occurs

The PTM upgrades the MOV at 0x1000 to a waypoint instruction and generates a waypoint update packet with address 0x1000 [a]. It then issues an exception branch address packet, indicating an IRQ, with a destination address of 0x0018, the IRQ vector address .

0x0018LDR PC, loads 0x3000Processor executes the instruction at the IRQ vector address. Traced as a normal indirect branch, with a branch address packet with a destination address of 0x3000.
-FIQ occurs

Last instruction, at 0x0018, was a waypoint instruction. Therefore the PTM traces the FIQ by issuing an exception branch address packet, indicating an FIQ, with a destination address of 0x001C, the FIQ vector address .

0x001CLDR PC, loads 0x2000The instruction at the FIQ vector address, traced as a normal indirect branch, with a branch address packet with a destination address of 0x2000.
0x2000(FIQ handler)Traced normally. Depending on the instruction stream and TraceEnable configuration, the PTM might generate some packets.
-
-
-
0x2100SUBS PC, R14, #4Return from FIQ handler, returns to the destination of the LDR PC at the IRQ vector address, 0x3000. PTM traces the return with a non-exception branch address packet with a destination address of 0x3000.
0x3000(IRQ handler)Traced normally. Depending on the instruction stream and TraceEnable configuration, the PTM might generate some packets.
-
-
-
0x3100SUBS PC, R14, #4Return from IRQ handler, returns to instruction after the last executed instruction. PTM traces the return with a non-exception branch address packet with a destination address of 0x1004.
0x1004MOV-

[a] If the PTM is holding any assembled atoms it outputs these in an atom header before generating the waypoint update packet. This means that the trace output stream has any outstanding atoms, followed by the waypoint update packet, followed by the exception branch address packet.


The second example shows the case where the instruction executed at the IRQ vector address is not a waypoint instruction. Table 5.5 shows this case, with the processor executing a NOP at the IRQ vector address before the FIQ occurs.

Table 5.5. Normal tracing of an FIQ after executing a NOP at the IRQ vector address

AddressInstructionTrace, if any, with explanation
0x1000MOVNonwaypoint instruction. Not traced when processor executes the instruction.
-IRQ occurs

The PTM upgrades the MOV at 0x1000 to a waypoint instruction and generates a waypoint update packet with the address 0x1000 [a]. It then issues an exception branch address packet, indicating an IRQ, with a destination address of 0x0018, the IRQ vector address .

0x0018NOP, 16-bit Thumb instructionProcessor executes the instruction at the IRQ vector address. This is not a waypoint instruction so the PTM does not generate any trace.
-FIQ occurs

The PTM upgrades the NOP at 0x0018 to a waypoint instruction and generates a waypoint update packet . It then issues an exception branch address packet, indicating an FIQ, with a destination address of 0x001C, the FIQ vector address .

0x001CLDR PC, loads 0x2000The instruction at the FIQ vector address, traced as a normal indirect branch, with a branch address packet with a destination address of 0x2000.
0x2000(FIQ handler)Traced normally. Depending on the instruction stream and TraceEnable configuration, the PTM might generate some packets.
-
-
-
0x2100SUBS PC, R14, #4Return from FIQ handler, returns to the instruction after the NOP at the IRQ vector address, therefore returns to 0x001A. PTM traces the return with a non-exception branch address packet with a destination address of 0x001A.
0x0001A(IRQ handler)Traced normally. Depending on the instruction stream and TraceEnable configuration, the PTM might generate some packets.
-
-
-
0x0100SUBS PC, R14, #4Return from IRQ handler, returns to instruction after the last executed instruction. PTM traces the return with a non-exception branch address packet with a destination address of 0x1004.
0x1004MOV-

[a] If the PTM is holding any assembled atoms it outputs these in an atom header before generating the waypoint update packet. This means that the trace output stream has any outstanding atoms, followed by the waypoint update packet, followed by the exception branch address packet.


Turning trace on between two back-to-back exceptions

Considering the case when an IRQ and an FIQ occur back-to-back, if you turn tracing on between the IRQ and the FIQ then the PTM generates an I-sync packet, with the address of the IRQ vector, followed by an exception branch address packet with a destination address of the FIQ vector address. It does not generate any waypoint update packet.

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