5.4. Waypoint update addresses

When the PTM must upgrade an instruction to a waypoint instruction, the address of the upgraded waypoint instruction depends on both the processor state when the exception occurred, and which exception occurred:

In these tables, LR is the address stored in the Link Register, LR (R14), for the exception.

Table 5.9. Waypoint update instruction addresses for exceptions in ARM state

ExceptionBase LRLRUpgraded instruction address
Reset---
Undefined InstructionInstruction address [a](Base LR) + 4Base LR
SVCInstruction address [a](Base LR) + 4Base LR
SMCInstruction address [a](Base LR) + 4Base LR
HVCInstruction address [a](Base LR) + 4Base LR
Data AbortAddress of aborted instruction(Base LR) + 8(Base LR) - 4
Prefetch AbortAddress of aborting instruction(Base LR) + 4(Base LR) - 4
IRQAddress of next instruction(Base LR) + 4(Base LR) - 4
FIQAddress of next instruction(Base LR) + 4(Base LR) - 4

[a] The address of the undefined instruction, or of the SVC, SMC, or HVC instruction.


Table 5.10. Waypoint update instruction addresses for exceptions in Thumb state

ExceptionBase LRLRUpgraded instruction address
Reset---
Undefined InstructionInstruction address [a](Base LR) + 2Base LR
SVCInstruction address [a](Base LR) + 2Base LR
SMCInstruction address [a](Base LR) + 4Base LR
HVCInstruction address [a](Base LR) + 4Base LR
Data AbortAddress of aborted instruction(Base LR) + 8(Base LR) - 2 or (Base LR) - 4 [b]
Prefetch AbortAddress of aborting instruction(Base LR) + 4(Base LR) - 2 or (Base LR) - 4
IRQAddress of next instruction(Base LR) + 4(Base LR) - 2 or (Base LR) - 4
FIQAddress of next instruction(Base LR) + 4(Base LR) - 2 or (Base LR) - 4
ThumbEE check-PC + 4(LR - 6) or (LR - 8)

[a] The address of the undefined instruction, or of the SVC, SMC, or HVC instruction.

[b] If the instruction referred to in the Base LR column is a 16-bit Thumb instruction then the address is (Base LR) - 2. See the text for more information about the value for 32-bit Thumb instructions.


In the following cases, it is implementation specific whether the upgraded waypoint instruction address is (Base LR) - 2 or (Base LR) - 4:

However, a decompressor does not have to determine the option that is implemented. For more information see:

Note

When an asynchronous abort occurs, the ARM architecture does not guarantee that execution of the program being traced completed up to the last waypoint address output before the exception branch address packet.

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