A.2. Summary of implementation defined PTM features

This section lists the PTM features that are implementation defined. It also indicates how you can check the actual implementation of each feature.

Table A.19 lists the PTM features where it is implementation defined either:

With all of these features the minimum permitted value is 0, indicating that the feature is not supported in the PTM implementation.

Table A.19. PTM features with implementation defined number of instances or size

FeaturePermitted valuesValue given by
Address comparators0-8 pairsBits [3:0] of the Configuration Code Register. [a]
EmbeddedICE watchpoint comparators0-8Bits [19:16] of the Configuration Code Extension Register. [b]
Context ID comparators0-3Bits [25:24] of the Configuration Code Register. [a]
VMID comparators0, 1Bit [26] of the Configuration Code Extension Register. [b]
Counters0-4Bits [15:13] of the Configuration Code Register. [a]
Sequencer0, 1Bit [16] of the Configuration Code Register. [a]
External inputs0-4Bits [19:17] of the Configuration Code Register. [a]
External outputs0-4Bits [22:20] of the Configuration Code Register. [a]
Extended external input bus width0-255Bits [10:3] of the Configuration Code Extension Register. [b]
Extended external input selectors0-4Bits [2:0] of the Configuration Code Extension Register. [b]
Instrumentation resources0-4Bits [15:13] of the Configuration Code Extension Register. [b]

Table A.20 lists the features that are optional in a PTM implementation. This means that it is implementation defined whether each of these features is supported.

Table A.20. Optional features in a PTM

Implementation ofCheck for support by
FIFOFULL controlReading bit [23] of the Configuration Code Register. [a] See also Checking support for implementation defined features.
Trace Start/Stop blockReading bit [26] of the Configuration Code Register. [a]
Trace all branchesTesting whether you can set bit [8] of the Main Control Register to 1. [b]
Cycle-accurate traceWriting 1 to bit [12] of the Main Control Register, see Checking support for implementation defined features.
EmbeddedICE behavior controlReading bit [21] of the Configuration Code Extension Register. [c]
EmbeddedICE inputs to Trace Start/Stop blockReading bit [20] of the Configuration Code Extension Register. [c]
OS Lock mechanismReading bit [0] of the OS Lock Status Register, see OS Lock Status Register, ETMOSLSR.
Return stackReading bit [23] of the Configuration Code Extension Register. [c]
TimestampingReading bit [22] of the Configuration Code Extension Register. [c]
Secure non-invasive debugReading bits [3:2] of the Authentication Status Register, see Authentication Status Register, ETMAUTHSTATUS.

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