A.1.1. Resource identification and event encoding

A PTM event is a Boolean combination of PTM resources. An event is encoded in a 17-bit Event Register as Figure A.1 shows.

Figure A.1. Writing to an Event Register

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table A.1 lists the encodings used for resources in Event Registers.

Table A.1. Resource identification encoding

Resource type [a]Index values [a]

Description of resource type

b000

0-15

Single address comparator.

b001

0-7

Address range comparison. Uses pairs of address comparators.

8-11

Instrumentation resource 1-4. Software-controlled resources, see Instrumentation resources.

b010

0-7

EmbeddedICE module watchpoint comparators.

b100

0-3

Counter at zero.

b101

0-2

3-7

8-10

11

12-14

15

Sequencer in states 1-3.

Reserved.

Context ID comparator 1-3.

VMID comparator.[b]

Reserved.

Trace start/stop resource.

b110

0-3

4-7

8-11

12

13

14

15

External inputs 1-4.

Reserved.

Extended external input selectors 1-4.

Reserved.

Processor is in Non-secure state.

Trace prohibited by processor.

Hard-wired resource, always TRUE.

[a] The Resource type is bits [6:4] of the 7-bit resource identifier, and the Index value is bits [3:0] of the identifier. Sometimes, the combined 7-bit resource identifier is called the Resource number.

[b] From PFTv1.1, and only in implementations that support Virtualization.


Table A.2 lists the encodings for the Boolean operations to be applied to the event resources.

Table A.2. Boolean function encoding for events

Encoding

Function

b000

A

b001

NOT(A)

b010

A AND B

b011

NOT(A) AND B

b100

NOT(A) AND NOT(B)

b101

A OR B

b110

NOT(A) OR B

b111

NOT(A) OR NOT(B)


Note

To permanently enable or disable an event, specify external input 16, using either function A or NOT (A).

Table A.3 lists the locations of the 17-bit Event Registers.

Table A.3. Locations of PTM event registers

Register numberOffset[a]Register
0x0020x008Trigger event, ETMTRIGGER
0x0080x020TraceEnable event, ETMTEEVR
0x0540x150Counter enable event for counter 1, ETMCNTENR1
0x0550x154Counter enable event for counter 2, ETMCNTENR2
0x0560x158Counter enable event for counter 3, ETMCNTENR3
0x0570x15CCounter enable event for counter 4, ETMCNTENR4
0x0580x160Counter reload event for counter 1, ETMCNTRLDEVR1
0x0590x164Counter reload event for counter 2, ETMCNTRLDEVR2
0x05A0x168Counter reload event for counter 3, ETMCNTRLDEVR3
0x05B0x16CCounter reload event for counter 4, ETMCNTRLDEVR4

0x060

0x180

Event for sequencer transition from state 1 to state 2, ETMSQ12EVR

0x061

0x184

Event for sequencer transition from state 2 to state 1, ETMSQ21EVR

0x062

0x188

Event for sequencer transition from state 2 to state 3, ETMSQ23EVR

0x063

0x18C

Event for sequencer transition from state 3 to state 1, ETMSQ31EVR

0x064

0x190

Event for sequencer transition from state 3 to state 2, ETMSQ32EVR

0x065

0x194

Event for sequencer transition from state 1 to state 3, ETMSQ13EVR

0x0680x1A0Event for external output 1, ETMEXTOUTEVR1
0x0690x1A4Event for external output 2, ETMEXTOUTEVR2
0x06A0x1A8Event for external output 3, ETMEXTOUTEVR3
0x06B0x1ACEvent for external output 4, ETMEXTOUTEVR4
0x07E0x1F8Timestamp event, ETMTSEVR

[a] When accessed in a memory-mapped scheme. The register offset is always (4 x (Register number)).


Copyright © 1999-2002, 2004-2008, 2011 ARM. All rights reserved.ARM IHI 0035B
Non-ConfidentialID060811