3.19.3. Memory-mapped accesses, PFTv1.0 SinglePower implementations

Table 3.84 shows the behavior of memory-mapped accesses in a SinglePower implementation in PFTv1.0. See PTM state definitions, PFTv1.0 SinglePower implementations for the meanings of the column headings.

Table 3.84. Memory-mapped accesses

RegisterPTM state 
No PowerOtherwise
Trace RegistersErrorOK[a], [b]
ETMLSRErrorOK
ETMLAR[c]ErrorOK
ETMPDSRErrorOK
ETMOSLSRErrorOK
ETMOSLARErrorOK[b]
ETMOSSRRErrorunp
ETMDEVID, ETMAUTHSTATUSErrorOK
Other ManagementErrorOK[b]
Reserved TraceErrorUNK/SBZP
Reserved ManagementErrorUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored

[b] When the CS Lock is set, these registers are WI.

[c] ETMLAR is not visible to Debugger accesses, so writes are ignored.


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