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Table 3.85 shows coprocessor access permissions for SinglePower implementations in PFTv1.0. See PTM state definitions, PFTv1.0 SinglePower implementations for the meanings of the column headings.
Table 3.85. Coprocessor accesses
| Register | PTM state | ||
|---|---|---|---|
| No Power | Non-Privileged | Otherwise | |
| Trace registers | NPoss | Error | OK[a] |
| ETMLSR | NPoss | Error | OK/RAZ |
| ETMLAR[b] | NPoss | Error | WI |
| ETMPDSR | NPoss | Error | OK |
| ETMOSLSR | NPoss | Error | OK |
| ETMOSLAR | NPoss | Error | OK |
| ETMOSSRR | NPoss | Error | unp |
| ETMDEVID, ETMAUTHSTATUS | NPoss | Error | OK |
| Other Management | NPoss | Error | OK |
| Reserved Trace | NPoss | Error | UNK/SBZP |
| Reserved Management | NPoss | Error | UNK/SBZP |
[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored [b] ETMLAR is not visible to Debugger accesses, so writes are ignored | |||
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