3.19.4. Coprocessor accesses, PFTv1.0 SinglePower implementations

Table 3.85 shows coprocessor access permissions for SinglePower implementations in PFTv1.0. See PTM state definitions, PFTv1.0 SinglePower implementations for the meanings of the column headings.

Table 3.85. Coprocessor accesses

RegisterPTM state
No PowerNon-PrivilegedOtherwise
Trace registersNPossErrorOK[a]
ETMLSRNPossErrorOK/RAZ
ETMLAR[b]NPossErrorWI
ETMPDSRNPossErrorOK
ETMOSLSRNPossErrorOK
ETMOSLARNPossErrorOK
ETMOSSRRNPossErrorunp
ETMDEVID, ETMAUTHSTATUSNPossErrorOK
Other ManagementNPossErrorOK
Reserved TraceNPossErrorUNK/SBZP
Reserved ManagementNPossErrorUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored

[b] ETMLAR is not visible to Debugger accesses, so writes are ignored


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