3.20.4. Coprocessor accesses, PFTv1.0 with multiple power implementations

Note

Coprocessor access to these registers is not possible when the core domain is powered down.

Table 3.88 shows coprocessor access permissions for full tracing implementations in PFTv1.0. See PTM state definitions, PFTv1.0 with multiple power implementations for the meanings of the column headings.

Table 3.88. Coprocessor accesses

RegisterPTM state
No Debug PowerNo Core PowerNon- PrivilegedSticky State SetOS Lock SetOtherwise
Trace registersErrorNPossErrorErrorErrorOK[a]
ETMLSRErrorNPossErrorOK/RAZOK/RAZOK/RAZ
ETMLAR[b]ErrorNPossErrorWIWIWI
ETMPDSRErrorNPossErrorOKOKOK
ETMOSLSRErrorNPossErrorOKOKOK
ETMOSLARErrorNPossErrorOKOKOK
ETMOSSRRErrorNPossErrorunpOKunp
ETMDEVID, ETMAUTHSTATUSErrorNPossErrorOKOKOK
Other ManagementErrorNPossErrorOKOKOK
Reserved TraceErrorNPossErrorunpunpUNK/SBZP
Reserved ManagementErrorNPossErrorUNK/SBZPUNK/SBZPUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored.

[b] ETMLAR is not visible to coprocessor accesses, so writes are ignored.


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