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Coprocessor access to these registers is not possible when the core domain is powered down.
Table 3.88 shows coprocessor access permissions for full tracing implementations in PFTv1.0. See PTM state definitions, PFTv1.0 with multiple power implementations for the meanings of the column headings.
Table 3.88. Coprocessor accesses
| Register | PTM state | |||||
|---|---|---|---|---|---|---|
| No Debug Power | No Core Power | Non- Privileged | Sticky State Set | OS Lock Set | Otherwise | |
| Trace registers | Error | NPoss | Error | Error | Error | OK[a] |
| ETMLSR | Error | NPoss | Error | OK/RAZ | OK/RAZ | OK/RAZ |
| ETMLAR[b] | Error | NPoss | Error | WI | WI | WI |
| ETMPDSR | Error | NPoss | Error | OK | OK | OK |
| ETMOSLSR | Error | NPoss | Error | OK | OK | OK |
| ETMOSLAR | Error | NPoss | Error | OK | OK | OK |
| ETMOSSRR | Error | NPoss | Error | unp | OK | unp |
| ETMDEVID, ETMAUTHSTATUS | Error | NPoss | Error | OK | OK | OK |
| Other Management | Error | NPoss | Error | OK | OK | OK |
| Reserved Trace | Error | NPoss | Error | unp | unp | UNK/SBZP |
| Reserved Management | Error | NPoss | Error | UNK/SBZP | UNK/SBZP | UNK/SBZP |
[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored. [b] ETMLAR is not visible to coprocessor accesses, so writes are ignored. | ||||||
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