3.21.2. Debugger accesses, PFTv1.1 SinglePower implementations

Table 3.89 shows the behavior of debugger accesses in a SinglePower implementation in PFTv1.1. See PTM state definitions, PFTv1.1 SinglePower implementations for the meanings of the column headings.

Table 3.89. Debugger accesses

RegisterPTM state
No PowerOtherwise
Trace registersErrorOK[a]
ETMLSRErrorOK/RAZ
ETMLAR[b]Errorunp
ETMPDSRErrorOK
ETMOSLSRErrorOK
ETMOSLARErrorOK
ETMOSSRRErrorunp

ETMDEVID, ETMAUTHSTATUS

ErrorOK
ETMITCTRLErrorOK
Other ManagementErrorOK
Reserved TraceErrorUNK/SBZP
Reserved ManagementErrorUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored

[b] ETMLAR is not visible to Debugger accesses, so accesses are unpredictable.


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