CoreSight Program Flow Trace Architecture SpecificationPFTv1.0 and PFTv1.1
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3.22.3. Memory-mapped accesses, PFTv1.1 with multiple power implementations

Table 3.93 shows the behavior of memory-mapped PTM register accesses in a PFTv1.1 implementation that has separate debug and core power domains. See PTM state definitions, PFTv1.1 with multiple power implementations for the meanings of the column headings.

Table 3.93. Memory-mapped accesses

Register

PTM state   
No Debug PowerNo Core PowerOS Lock SetOtherwise
Trace registersErrorErrorOK[d], [a]OK[b], [d]
ETMLSRErrorOKOKOK
ETMLARErrorOKOKOK
ETMPDSRErrorOK[c]OK[c]OK[c]
ETMOSLSRErrorOKOKOK
ETMOSLARErrorErrorOK[d]OK[d]
ETMOSSRRErrorunpunpunp

ETMDEVID, ETMAUTHSTATUS

ErrorOK[d]OK[d]OK[d]
ETMITCTRLErrorimpdefimpdefOK[d]
Other ManagementErrorOK[d]OK[d]OK[d]
Reserved TraceErrorError

UNK/SBZP

UNK/SBZP

Reserved ManagementError

UNK/SBZP

UNK/SBZP

UNK/SBZP

[a] When the OS Lock is set, Trace registers must always be writeable regardless of the value of ETM_PD.

[b] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored.

[c] When the CS Lock is set, reads from the ETMPDSR do not clear the Sticky State.

[d] When the CS Lock is set, these registers are WI.


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