3.22.4. Coprocessor accesses, PFTv1.1 with multiple power implementations

Note

Coprocessor access to these registers is not possible when the core domain is powered down.

Table 3.94 shows coprocessor access permissions for multiple power implementations in PFTv1.1. See PTM state definitions, PFTv1.1 with multiple power implementations for the meanings of the column headings.

Table 3.94. Coprocessor accesses

RegisterPTM state   
No Core PowerNon- PrivilegedOS Lock SetOtherwise[a]
Trace registersNPossErrorOK[b]OK[c]
ETMLSRNPossErrorunpunp
ETMLAR[d]NPossErrorunpunp
ETMPDSRNPossErrorunpunp
ETMOSLSRNPossErrorOKOK
ETMOSLARNPossErrorOKOK
ETMOSSRRNPossErrorunpunp
ETMDEVID, ETMAUTHSTATUSNPossErrorOKOK
ETMITCTRLNPossErrorunpunp
Other ManagementNPossErrorunpunp
Reserved TraceNPossErrorUNK/SBZPUNK/SBZP
Reserved ManagementNPossErrorunpunp

[a] These settings also apply to the No Debug Power state. This allows the ETM state to be saved and restored, and the ETM to be configured, when parts of the ETM are powered down.

[b] When the OS Lock is set, Trace registers must always be writeable regardless of the value of ETM_PD.

[c] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored.

[d] ETMLAR is not visible to coprocessor accesses, so writes are ignored.


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