CoreSight Program Flow Trace Architecture SpecificationPFTv1.0 and PFTv1.1
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CoreSight™ Program Flow Trace™ Architecture Specification

PFTv1.0 and PFTv1.1

Copyright © 1999-2002, 2004-2008, 2011 ARM. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this specification
Product revision status
Intended audience
Using this specification
Conventions
Further reading
Feedback
Feedback on the Program Flow Trace architecture
Feedback on this specification
1. Introduction
1.1. About the Program Trace Macrocell
1.1.1. Structure of a PTM
1.1.2. The debug environment
1.1.3. Thumb, ThumbEE, and Java support
1.1.4. Connections to a PTM
1.1.5. Trace compression
1.1.6. Resets
2. Program Flow Tracing
2.1. About Program Flow Tracing
2.1.1. Tracing branches
2.1.2. Tracing exceptions
2.1.3. Nonwaypoint instructions
2.1.4. PFT trace example
2.2. Waypoint instructions
2.2.1. Unpredictable encodings
2.3. Upgrading a nonwaypoint instruction on an exception
2.4. Timestamping
2.5. Virtualization
3. Program Trace Macrocell Programmers Model
3.1. About the PTM programmers model
3.2. CoreSight support
3.2.1. Programmers model requirements
3.2.2. Topology detection requirements
3.3. TraceEnable
3.3.1. About TraceEnable
3.3.2. TraceEnable rules
3.3.3. The TraceEnable start/stop block
3.3.4. TraceEnable Include/exclude control
3.4. Address comparators
3.4.1. General behavior of address comparators
3.4.2. Single address comparators (SACs)
3.4.3. Address range comparators (ARCs)
3.5. Context ID comparators
3.6. Virtual Machine ID comparator
3.7. EmbeddedICE watchpoint comparator inputs
3.7.1. EmbeddedICE watchpoint comparator input behavior
3.7.2. Default behavior of EmbeddedICE watchpoint comparator inputs
3.7.3. Pulse and latch behavior of EmbeddedICE watchpoint comparator inputs
3.7.4. Examples of using EmbeddedICE watchpoint comparator inputs
3.8. Event resources and PTM events
3.8.1. The PTM event resources
3.8.2. Example PTM resource configuration
3.8.3. Defining a PTM event
3.8.4. Summary of the PTM events
3.9. PTM counters
3.9.1. Use of PTM counters
3.10. The PTM sequencer
3.10.1. Use of the PTM sequencer
3.11. Instrumentation resources
3.11.1. The Instrumentation resource event resources
3.11.2. Instructions for controlling the Instrumentation resources
3.11.3. Instrumentation resource behavior when tracing parallel execution
3.12. PTM input resources
3.12.1. External inputs
3.12.2. Extended external inputs
3.12.3. Non-secure state resource
3.12.4. Trace prohibited resource
3.12.5. Hard-wired TRUE resource
3.13. PTM external outputs
3.14. Triggering a trace run
3.15. About the PTM registers
3.15.1. Register short names
3.15.2. PTM trace and PTM management registers
3.15.3. Accessing the PTM registers
3.15.4. Use of the Programming bit
3.15.5. Synchronization of PTM register updates
3.15.6. Organization of the PTM registers
3.16. PTM register descriptions
3.16.1. Main Control Register, ETMCR
3.16.2. Configuration Code Register, ETMCCR
3.16.3. Trigger Event Register, ETMTRIGGER
3.16.4. Status Register, ETMSR
3.16.5. System Configuration Register, ETMSCR
3.16.6. About the TraceEnable control registers
3.16.7. TraceEnable Start/Stop Control Register, ETMTSSCR
3.16.8. TraceEnable Event Register, ETMTEEVR
3.16.9. TraceEnable Control Register, ETMTECR1
3.16.10. FIFOFULL Level Register, ETMFFLR
3.16.11. About the address comparator registers
3.16.12. Address Comparator Value Registers, ETMACVRn
3.16.13. Address Comparator Access Type Registers, ETMACTRn
3.16.14. About the counter registers
3.16.15. Counter Reload Value Registers, ETMCNTRLDVRn
3.16.16. Counter Enable Event Registers, ETMCNTENRn
3.16.17. Counter Reload Event Registers, ETMCNTRLDEVRn
3.16.18. Counter Value Registers, ETMCNTVRn
3.16.19. About the sequencer registers
3.16.20. Sequencer State Transition Event Registers, ETMSQabEVR
3.16.21. Current Sequencer State Register, ETMSQR
3.16.22. External Output Event Registers, ETMEXTOUTEVRn
3.16.23. About the Context ID comparator registers
3.16.24. Context ID Comparator Value Registers, ETMCIDCVRn
3.16.25. Context ID Comparator Mask Register, ETMCIDCMR
3.16.26. Implementation specific registers, ETMIMPSPEC0 to ETMIMPSPEC7
3.16.27. Synchronization Frequency Register, ETMSYNCFR
3.16.28. ID Register, ETMIDR
3.16.29. Configuration Code Extension Register, ETMCCER
3.16.30. Extended External Input Selection Register, ETMEXTINSELR
3.16.31. TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR
3.16.32. EmbeddedICE Behavior Control Register, ETMEIBCR
3.16.33. Timestamp Event Register, ETMTSEVR
3.16.34. Auxiliary Control Register, ETMAUXCR
3.16.35. CoreSight Trace ID Register, ETMTRACEIDR
3.16.36. VMID Comparator Value Register, ETMVMIDCVR
3.16.37. About the Operating System Save and Restore registers
3.16.38. OS Lock Access Register, ETMOSLAR
3.16.39. OS Lock Status Register, ETMOSLSR
3.16.40. OS Save and Restore Register, ETMOSSRR
3.16.41. Device Power-Down Control Register, ETMPDCR
3.16.42. Device Power-Down Status Register, ETMPDSR
3.16.43. Integration Mode Control Register, ETMITCTRL
3.16.44. About the claim tag registers
3.16.45. Claim Tag Set Register, ETMCLAIMSET
3.16.46. Claim Tag Clear Register, ETMCLAIMCLR
3.16.47. About the lock registers
3.16.48. Lock Access Register, ETMLAR
3.16.49. Lock Status Register, ETMLSR
3.16.50. Authentication Status Register, ETMAUTHSTATUS
3.16.51. Device Configuration Register, ETMDEVID
3.16.52. Device Type Register, ETMDEVTYPE
3.16.53. About the Peripheral Identification Registers
3.16.54. Peripheral ID0 Register, ETMPIDR0
3.16.55. Peripheral ID1 Register, ETMPIDR1
3.16.56. Peripheral ID2 Register, ETMPIDR2
3.16.57. Peripheral ID3 Register, ETMPIDR3
3.16.58. Peripheral ID4 Register, ETMPIDR4
3.16.59. Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR7
3.16.60. About the Component Identification Registers
3.16.61. Component ID0 Register, ETMCIDR0
3.16.62. Component ID1 Register, ETMCIDR1
3.16.63. Component ID2 Register, ETMCIDR2
3.16.64. Component ID3 Register, ETMCIDR3
3.17. Power-down support
3.17.1. Power down support in PFTv1.0
3.17.2. Power down support from PFTv1.1
3.17.3. PTM behavior when the OS Lock is set
3.17.4. Guidelines for the PTM trace registers to be saved and restored
3.18. About the access permissions for PTM registers
3.18.1. Access types
3.18.2. Meanings of terms and abbreviations used in this section
3.18.3. Restrictions on accesses using a Direct JTAG connection
3.18.4. Effect of DBGSWENABLE on register access
3.19. Access permissions for PFTv1.0 SinglePower implementations
3.19.1. PTM state definitions, PFTv1.0 SinglePower implementations
3.19.2. Debugger accesses, PFTv1.0 SinglePower implementations
3.19.3. Memory-mapped accesses, PFTv1.0 SinglePower implementations
3.19.4. Coprocessor accesses, PFTv1.0 SinglePower implementations
3.20. Access permissions for PFTv1.0 with multiple power implementations
3.20.1. PTM state definitions, PFTv1.0 with multiple power implementations
3.20.2. Debugger accesses, PFTv1.0 with multiple power implementations
3.20.3. Memory-mapped accesses, PFTv1.0 with multiple power implementations
3.20.4. Coprocessor accesses, PFTv1.0 with multiple power implementations
3.21. Access permissions for PFTv1.1 SinglePower implementations
3.21.1. PTM state definitions, PFTv1.1 SinglePower implementations
3.21.2. Debugger accesses, PFTv1.1 SinglePower implementations
3.21.3. Memory-mapped accesses, PFTv1.1 SinglePower implementations
3.21.4. Coprocessor accesses, PFTv1.1 SinglePower implementations
3.22. Access permissions for PFTv1.1 with multiple power implementations
3.22.1. PTM state definitions, PFTv1.1 with multiple power implementations
3.22.2. Debugger accesses, PFTv1.1 with multiple power implementations
3.22.3. Memory-mapped accesses, PFTv1.1 with multiple power implementations
3.22.4. Coprocessor accesses, PFTv1.1 with multiple power implementations
3.23. Programming the PTM to trace all execution
4. Program Flow Trace Protocol 
4.1. About the Program Flow Trace protocol
4.2. PFT atoms
4.3. Summary of PFT packets
4.4. Cycle-accurate tracing
4.5. PFT packet formats
4.5.1. A-sync, alignment synchronization packet
4.5.2. I-sync, instruction synchronization packet
4.5.3. Atom packet
4.5.4. Branch address packet
4.5.5. Waypoint update packet
4.5.6. Trigger packet
4.5.7. Context ID packet
4.5.8. VMID packets
4.5.9. Timestamp packet
4.5.10. Exception return packet
4.5.11. Ignore packet
4.6. Branch broadcasting
4.7. Prohibited regions
4.7.1. Behavior of the PTM when the processor is in a prohibited region
4.7.2. Non-invasive debug disabled
4.8. Trace FIFO overflow
4.9. Wait for Interrupt and Wait for Event
4.10. Large blocks of instructions
4.11. Synchronization
4.11.1. Periodic synchronization
4.11.2. Alignment synchronization
4.11.3. Instruction synchronization
4.11.4. Timestamp synchronization
4.12. Tracing security state changes
4.12.1. Changing from Non-secure to Secure state
4.12.2. Changing from Secure to Non-secure state
4.13. Use of a return stack
4.14. Timestamping
4.15. Trace flushing
4.15.1. CoreSight or other ATB flush request
4.15.2. Setting the Programming bit or the OS Lock
4.15.3. WFI or WFE request
4.16. Tracing Thumb instructions
4.16.1. 32-bit Thumb instructions
4.16.2. Thumb CBZ and CBNZ instructions
4.17. Jazelle state
4.18. Debug state
5. Tracing Exceptions
5.1. About exception tracing in the PFT architecture
5.2. The different exception cases
5.2.1. Exception occurs after a nonwaypoint instruction
5.2.2. Exception occurs immediately after a waypoint instruction
5.2.3. Exception occurs immediately after another exception
5.2.4. Exception occurs immediately after trace turn-on
5.3. Tracing the different exception types
5.3.1. Processor reset exception
5.3.2. Undefined Instruction exception
5.3.3. SVC (Supervisor Call) or SMC (Secure Monitor Call) exception
5.3.4. Prefetch Abort exception
5.3.5. Synchronous Data Abort exception
5.3.6. Asynchronous Data Abort, FIQ or IRQ exception
5.3.7. Entry to Hyp mode
5.3.8. Debug state entry, when Halting debug-mode is enabled
5.3.9. ThumbEE check that goes to a handler, including the CHKA instruction
5.3.10. Jazelle exception that goes to an ARM or Thumb state handler
5.3.11. Secure to Non-secure state change
5.3.12. Other exceptions
5.4. Waypoint update addresses
A. PTM Quick Reference Information
A.1. PTM event resources
A.1.1. Resource identification and event encoding
A.1.2. Resource control registers
A.2. Summary of implementation defined PTM features
B. Trace Decompressor Operation
B.1. About PTM trace decompression
B.2. PFT trace state and objects
B.2.1. PFT state information
B.2.2. PFT output objects
B.3. PFT trace decompression flow
B.3.1. Overall PFT trace decompression flow
B.3.2. Details of PFT trace decompression operations
C. Software Issues for PFT
C.1. About tracing dynamically-loaded code
C.1.1. Simple overlay support
C.2. Software support for Context ID
C.3. Hardware support for Context ID
D. Architecture Version Information
D.1. PFTv1.0 to PFTv1.1
D.1.1. Programmers model
D.1.2. Signal protocol
Glossary

List of Figures

1.1. Example debugging environment
1.2. Main connections to a PTM
3.1. The TraceEnable mechanism
3.2. Programming the TraceEnable logic
3.3. Example resource configuration
3.4. Address comparator match filtering from PFTv1.1
3.5. Defining a PTM event
3.6. Sequencer state diagram
3.7. Thumb encodings
3.8. ARM encodings
3.9. Extended external inputs implementation example
3.10. Mapping from register number to CP14 MRC or MCR instruction fields
3.11. Programming PTM registers
3.12. ETMCR bit assignments
3.13. ETMCCR bit assignments
3.14. ETMTRIGGER bit assignments
3.15. ETMSR bit assignments
3.16. ETMSCR bit assignments
3.17. ETMTSSCR bit assignments
3.18. ETMTEEVR bit assignments
3.19. ETMTECR1 bit assignments
3.20. ETMFFLR bit assignments
3.21. ETMACVR bit assignments
3.22. ETMACTR bit assignments from PFTv1.1
3.23. ETMACTR bit assignments, PFTv1.0
3.24. ETMCNTRLDVR bit assignments
3.25. ETMCNTENR bit assignments
3.26. ETMCNTRLDEVR bit assignments
3.27. ETMCNTVR bit assignments
3.28. ETMSQabEVR bit assignments
3.29. ETMSQR bit assignments
3.30. ETMEXTOUTEVR bit assignments
3.31. ETMCIDCVR bit assignments
3.32. ETMCIDCMR bit assignments
3.33. Implementation specific Register 0 bit assignments
3.34. ETMSYNCFR bit assignments
3.35. ETMIDR bit assignments
3.36. ETMCCER bit assignments
3.37. ETMEXTINSELR bit assignments
3.38. ETMTESSEICR bit assignments
3.39. ETMEIBCR bit assignments
3.40. ETMTSEVR bit assignments
3.41. ETMTRACEIDR bit assignments
3.42. ETMVMIDCVR bit assignments
3.43. ETMOSLAR bit assignments
3.44. ETMOSLSR bit assignments
3.45. ETMOSSRR bit assignments
3.46. ETMPDCR bit assignments
3.47. ETMPDSR bit assignments
3.48. ETMITCTRL bit assignments
3.49. ETMCLAIMSET bit assignments
3.50. ETMCLAIMCLR bit assignments
3.51. ETMLAR bit assignments
3.52. ETMLSR bit assignments
3.53. ETMAUTHSTATUS bit assignments
3.54. Secure non-invasive debug enable logic when controlled by the PTM
3.55. ETMDEVID bit assignments
3.56. ETMDEVTYPE bit assignments
3.57. Mapping between the Peripheral ID Registers and the Peripheral ID value
3.58. Peripheral ID fields for an ARM implementation
3.59. ETMPIDR0 bit assignments
3.60. ETMPIDR1 bit assignments
3.61. ETMPIDR2 bit assignments
3.62. ETMPIDR3 bit assignments
3.63. ETMPIDR4 bit assignments
3.64. ETMPIDR5 to ETMPIDR7 bit assignments
3.65. Mapping between the Component ID Registers and the Component ID value
3.66. ETMCIDR0 bit assignments
3.67. ETMCIDR1 bit assignments
3.68. ETMCIDR2 bit assignments
3.69. ETMCIDR3 bit assignments
4.1. A-sync alignment synchronization packet
4.2. I-sync instruction synchronization packet, PFTv1.1
4.3. Atom packet, cycle-accurate tracing not enabled
4.4. Cycle-accurate atom packet
4.5. Full branch address packet with exception, ARM state
4.6. Full branch address packet with exception, Thumb state
4.7. Full branch address packet with exception, Jazelle state
4.8. Branch address packet cycle count bytes, when cycle-accurate tracing is enabled
4.9. Address bytes when bit [11] is the most significant bit that changes, in Thumb state
4.10. Branch to Thumb state with change in A[6:1], no exception information byte
4.11. Branch to Thumb state with change in A[12:7], no exception information byte
4.12. Branch to Thumb state with change in A[19:13], no exception information byte
4.13. Branch to Thumb state with change in A[26:20], no exception information byte
4.14. Branch to Thumb state with change in A[31:27], no exception information byte
4.15. Branch to Thumb state with change in A[12:1], with exception information byte
4.16. Branch to Thumb state with change in A[12:1], with two exception information bytes
4.17. Branch to Thumb state with change in A[19:13], with exception information byte
4.18. Branch to Thumb state with change in A[26:20], with exception information byte
4.19. Branch to Thumb state with change in A[31:27], with exception information byte
4.20. Branch to ARM state with change in A[7:2], no exception information byte
4.21. Branch to ARM state with change in A[13:8], no exception information byte
4.22. Branch to ARM state with change in A[20:14], no exception information byte
4.23. Branch to ARM state with change in A[27:21], no exception information byte
4.24. Branch to ARM state with change in A[31:28], no exception information byte
4.25. Branch to ARM state with change in A[13:2], with exception information byte
4.26. Branch to ARM state with change in A[20:14], with exception information byte
4.27. Branch to ARM state with change in A[27:21], with exception information byte
4.28. Branch to ARM state with change in A[31:28], with exception information byte
4.29. Cycle count bytes when bit [13] is the MS nonzero bit
4.30. Cycle count byte when MS nonzero bit is in Count[3:0]
4.31. Cycle count bytes when MS nonzero bit is in Count[10:4]
4.32. Cycle count bytes when MS nonzero bit is in Count[17:11]
4.33. Cycle count bytes when MS nonzero bit is in Count[24:18]
4.34. Cycle count bytes when MS nonzero bit is in Count[31:25]
4.35. Waypoint update packet, ARM state
4.36. Waypoint update packet, Thumb state
4.37. Trigger packet
4.38. Context ID packet
4.39. VMID packet
4.40. 48-bit timestamp packet
4.41. 48-bit timestamp packet in cycle-accurate mode
4.42. 64-bit timestamp packet
4.43. 64-bit timestamp packet in cycle-accurate mode
4.44. Exception return packet
4.45. Ignore packet
A.1. Writing to an Event Register
B.1. Trace decompression operation
C.1. SRAM overlay examples
C.2. Memory map and overlay physical address space

List of Tables

2.1. PTM trace example
2.2. Direct branches, ARM instruction set
2.3. Direct branches, Thumb and ThumbEE instruction sets
2.4. Indirect branches, ARM instruction set
2.5. Indirect branches, Thumb and ThumbEE instruction sets
3.1. Required PTM logical interfaces
3.2. Permitted instruction block end addresses
3.3. Definition of ARCs by Address Comparator Value Registers
3.4. Default behavior of EmbeddedICE watchpoint comparator inputs
3.5. Event resource definitions
3.6. Additional information about the PTM event resources
3.7. Boolean operations for defining PTM events
3.8. Defining a PTM event
3.9. The PTM event registers
3.10. The Instrumentation resource event resources
3.11. Hint field encodings for the Instrumentation instructions
3.12. Instrumentation resource parallel execution examples, for two instructions
3.13. Examples of register short names
3.14. Split of PTM register map into trace and management registers
3.15. Typical PTM register access implementations
3.16. PTM registers summary
3.17. ETMCR bit assignments
3.18. ETMCCR bit assignments
3.19. ETMTRIGGER bit assignments
3.20. ETMSR bit assignments
3.21. ETMSCR bit assignments
3.22. ETMTSSCR bit assignments
3.23. ETMTEEVR bit assignments
3.24. ETMTECR1 bit assignments
3.25. ETMFFLR bit assignments
3.26. ETMACVR bit assignments
3.27. ETMACTR bit assignments
3.28. Address comparator filtering by state and mode, PFTv1.1 with Security Extensions
3.29. Address comparator filtering by state and mode, PFTv1.1, no Security Extensions
3.30. Summary of Counter registers
3.31. ETMCNTRLDVR bit assignments
3.32. ETMCNTENR bit assignments
3.33. ETMCNTRLDEVR bit assignments
3.34. ETMCNTVR bit assignments
3.35. Sequencer register allocation
3.36. ETMSQabEVR bit assignments
3.37. ETMSQR bit assignments
3.38. ETMEXTOUTEVR bit assignments
3.39. Summary of the Context ID comparator registers
3.40. ETMCIDCVR bit assignments
3.41. ETMCIDCMR bit assignments
3.42. Implementation specific Register 0 bit assignments
3.43. ETMSYNCFR bit assignments
3.44. ETMIDR bit assignments
3.45. ETMCCER bit assignments
3.46. ETMEXTINSELR bit assignments
3.47. ETMTESSEICR bit assignments
3.48. ETMEIBCR bit assignments
3.49. ETMTSEVR bit assignments
3.50. ETMTRACEIDR bit assignments
3.51. ETMVMIDCVR bit assignments
3.52. ETMOSLAR bit assignments
3.53. ETMOSLSR bit assignments
3.54. OS lock implementation
3.55. ETMOSSRR bit assignments
3.56. ETMPDCR bit assignments
3.57. ETMPDSR bit assignments
3.58. ETMPDSR encodings
3.59. ETMITCTRL bit assignments
3.60. ETMCLAIMSET bit assignments
3.61. ETMCLAIMCLR bit assignments
3.62. ETMLAR bit assignments
3.63. ETMLSR bit assignments
3.64. ETMAUTHSTATUS bit assignments
3.65. Implementation of the Secure non-invasive debug field
3.66. ETMDEVID bit assignments
3.67. ETMDEVTYPE bit assignments
3.68. Summary of the peripheral identification registers
3.69. Register fields for the Peripheral ID registers
3.70. ETMPIDR0 bit assignments
3.71. ETMPIDR1 bit assignments
3.72. ETMPIDR2 bit assignments
3.73. ETMPIDR3 bit assignments
3.74. ETMPIDR4 bit assignments
3.75. ETMPIDR5 to ETMPIDR7 bit assignments
3.76. Summary of the component identification registers
3.77. ETMCIDR0 bit assignments
3.78. ETMCIDR1 bit assignments
3.79. ETMCIDR2 bit assignments
3.80. ETMCIDR3 bit assignments
3.81. Determining the level of power down support
3.82. Typical list of PTM registers to be saved and restored
3.83. Debugger accesses
3.84. Memory-mapped accesses
3.85. Coprocessor accesses
3.86. Debugger accesses
3.87. Memory-mapped accesses
3.88. Coprocessor accesses
3.89. Debugger accesses
3.90. Memory-mapped accesses
3.91. Coprocessor accesses
3.92. Debugger accesses
3.93. Memory-mapped accesses
3.94. Coprocessor accesses
4.1. Packet formats
4.2. Cycle count example with late trace turn-on
4.3. Atom header encoding when cycle-accurate tracing is not enabled
4.4. Values of Exception[3:0] for ARMv7-A and ARMv7-R processors
4.5. Number of address bytes generated for branch address packets
4.6. Interpretation of bit [7] in address byte 0
4.7. Interpretation of bits [7:6] in the address bytes 1-4
4.8. Number cycle count bytes generated for branch address packets
4.9. Permitted waypoint address outputs in waypoint update packets
4.10. Tracing a change of Context ID
4.11. Exception return instructions
4.12. Branch with link instructions
4.13. PTM branch tracing when using the return stack
5.1. Tracing an exception occurring after execution of a nonwaypoint instruction
5.2. Tracing an exception immediately after execution of a waypoint instruction
5.3. Tracing back-to-back exceptions
5.4. Normal tracing of an FIQ after executing a branch at the IRQ vector address
5.5. Normal tracing of an FIQ after executing a NOP at the IRQ vector address
5.6. Descriptions of how a PTM traces different exceptions
5.7. Tracing a synchronous Data Abort exception after a waypoint instruction
5.8. Tracing a synchronous Data Abort exception after a nonwaypoint instruction
5.9. Waypoint update instruction addresses for exceptions in ARM state
5.10. Waypoint update instruction addresses for exceptions in Thumb state
A.1. Resource identification encoding
A.2. Boolean function encoding for events
A.3. Locations of PTM event registers
A.4. Trace Start/Stop Resource Control Register, 0x006
A.5. TraceEnable Control Register, 0x009
A.6. FIFOFULL Level Register, 0x00B
A.7. Address Comparator Value Registers, 0x010-0x01F
A.8. Address Comparator Access Type Registers, 0x020-0x02F, PFTv1.0
A.9. Address Comparator Access Type Registers, 0x020-0x02F, PFTv1.1
A.10. Counter Reload Value Registers, 0x050-0x053
A.11. Counter Value Registers, 0x05C-0x05F
A.12. Current Sequencer State Register, 0x067
A.13. Locations of the Context ID Comparator Value Registers
A.14. Context ID Comparator Value Registers, 0x06C-0x06E
A.15. Context ID Comparator Mask Register, 0x06F
A.16. VMID Comparator Value Register, 0x090, from PFTv1.1
A.17. Synchronization Frequency Register, 0x078
A.18. Extended External Input Selection Register, 0x07B
A.19. PTM features with implementation defined number of instances or size
A.20. Optional features in a PTM

Proprietary Notice

ARM, the ARM Powered logo, Jazelle, RealView and Thumb are registered trademarks of ARM Limited.

The ARM logo, AMBA, CoreSight, EmbeddedICE, and ETM, are trademarks of ARM Limited.

All other products or services mentioned herein may be trademarks of their respective owners.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith.

1. Subject to the provisions set out below, ARM hereby grants to you a perpetual, non-exclusive, nontransferable, royalty free, worldwide licence to use this ARM Program Flow Trace Architecture Specification for the purposes of developing; (i) software applications or operating systems which are targeted to run on microprocessor cores distributed under licence from ARM; (ii) tools which are designed to develop software programs which are targeted to run on microprocessor cores distributed under licence from ARM; (iii) integrated circuits which incorporate a microprocessor core manufactured under licence from ARM.

2. Except as expressly licensed in Clause 1 you acquire no right, title or interest in the ARM Program Flow Trace Architecture Specification, or any Intellectual Property therein. In no event shall the licences granted in Clause 1, be construed as granting you expressly or by implication, estoppel or otherwise, licences to any ARM technology other than the ARM Program Flow Trace Architecture Specification. The licence grant in Clause 1 expressly excludes any rights for you to use or take into use any ARM patents. No right is granted to you under the provisions of Clause 1 to; (i) use the ARM Program Flow Trace Architecture Specification for the purposes of developing or having developed microprocessor cores or models thereof which are compatible in whole or part with either or both the instructions or programmers’ models described in this ARM Program Flow Trace Architecture Specification; or (ii) develop or have developed models of any microprocessor cores designed by or for ARM; or (iii) distribute in whole or in part this ARM Program Flow Trace Architecture Specification to third parties without the express written permission of ARM; or (iv) translate or have translated this ARM Program Flow Trace Architecture Specification into any other languages.

3. THE ARM PROGRAM FLOW TRACE ARCHITECTURE SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE.

4. No licence, express, implied or otherwise, is granted to LICENSEE, under the provisions of Clause 1, to use the ARM tradename, in connection with the use of the ARM Program Flow Trace Architecture Specification or any products based thereon. Nothing in Clause 1 shall be construed as authority for you to make any representations on behalf of ARM in respect of the ARM Program Flow Trace Architecture Specification or any products based thereon.

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A09 April 2008First release for v1.0
Revision B31 March 2011First release for v1.1
Copyright © 1999-2002, 2004-2008, 2011 ARM. All rights reserved.ARM IHI 0035B
Non-ConfidentialID060811
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