ARM® Generic Interrupt Controller Architecture Specification: 4.1.2. Distributor register map

4.1.2. Distributor register map

Table 4.1 shows the Distributor register map. Address offsets are relative to the Distributor base address defined by the GIC system memory map.

All GIC registers are 32-bits wide. Reserved register addresses are RAZ/WI.

Table 4.1. Distributor register map

Offset	Name ^[1]	Type	Reset ^[2]	Description
`0x000`	ICDDCR	RW	`0x0000 0000`	Distributor Control Register (ICDDCR)
`0x004`	ICDICTR	RO	implementation defined	Interrupt Controller Type Register (ICDICTR)
`0x008`	ICDIIDR	RO	implementation defined	Distributor Implementer Identification Register (ICDIIDR)
`0x00C`-`0x07C`	-	-	-	Reserved
`0x080`	ICDISR	RW	implementation defined ^[3]	Interrupt Security Registers (ICDISRn)^[4]
`0x084`-`0x0FC`	ICDISR	RW	`0x0000 0000`	Interrupt Security Registers (ICDISRn)^[4]
`0x100`-`0x17C`	ICDISER	RW	implementation defined	Interrupt Set-Enable Registers (ICDISERn)
`0x180`-`0x1FC`	ICDICER	RW	implementation defined	Interrupt Clear-Enable Registers (ICDICERn)
`0x200`-`0x27C`	ICDISPR	RW	`0x0000 0000`	Interrupt Set-Pending Registers (ICDISPRn)
`0x280`-`0x2FC`	ICDICPR	RW	`0x0000 0000`	Interrupt Clear-Pending Registers (ICDICPRn)
`0x300`-`0x37C`	ICDABR	RO	`0x0000 0000`	Active Bit Registers (ICDABRn)
`0x380`-`0x3FC`	-	-	-	Reserved
`0x400`-`0x7F8`	ICDIPR	RW	`0x0000 0000`	Interrupt Priority Registers (ICDIPRn)
`0x7FC`	-	-	-	Reserved
`0x800`-`0x81C`	ICDIPTR	RO ^[5]	implementation defined	Interrupt Processor Targets Registers (ICDIPTRn)
`0x820`-`0xBF8`	ICDIPTR	RW ^[5]	`0x0000 0000`	Interrupt Processor Targets Registers (ICDIPTRn)
`0xBFC`	-	-	-	Reserved
`0xC00`-`0xCFC`	ICDICFR	RW	implementation defined	Interrupt Configuration Registers (ICDICFRn)
`0xD00`-`0xDFC`	-	-	-	implementation defined registers
`0xE00`-`0xEFC`	-	-	-	Reserved
`0xF00`	ICDSGIR	WO	-	Software Generated Interrupt Register (ICDSGIR)
`0xF04`-`0xFCC`	-	-	-	Reserved
`0xFD0`-`0xFFC`	-	RO	implementation defined	Identification registers
^[1]For legacy shortform register names see Appendix C Register Shortform Names. ^[2]For details of any restrictions that apply to the reset values of implementation defined cases, for example architecturally-required bit values, see the appropriate register description. ^[3]For more information see ICDISR0 reset value. ^[4]Present only if the GIC implements the Security Extensions, otherwise RAZ/WI. ^[5]In a uniprocessor implementation, these registers are RAZ/WI.

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