ARM® Generic Interrupt Controller Architecture Specification: 3.4. The effect of the Security Extensions on interrupt handling

3.4. The effect of the Security Extensions on interrupt handling

If a GIC CPU interface implements the Security Extensions, it provides two interrupt output signals, IRQ and FIQ:

The CPU interface always uses the IRQ exception request for Non-secure interrupts
Software can configure the CPU interface to use either IRQ or FIQ exception requests for Secure interrupts.

Note

In a GIC that does not support the Security Extensions, each CPU interface implements only a single port for signalling interrupts to a target processor. The alternatives for providing GIC interrupt routing for both IRQ and FIQ exception requests in a processor environment that does not include the Security Extensions are:

Implement two instances of the GIC, without the Security Extensions. One instance routes FIQs and the other instance routes IRQs.
Implement a single GIC that implements the Security Extensions, and implements the CPU interface to the processor so that all accesses appear to the GIC as Secure accesses. In an implementation of this model, software configures an interrupt as Secure to assign it to the generation of FIQ exception requests to the processor.

The remainder of this section describes a GIC that implements the Security Extensions.

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