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The ICDISR characteristics are:
The ICDISRs provide a Security status bit for each interupt supported by the GIC. Each bit controls the security status of the corresponding interrupt.
Accessible by Secure accesses only. The register addresses are RAZ/WI to Non-secure accesses.
A register bit corresponding to an unimplemented interrupt is RAZ/WI.
If the GIC implements configuration lockdown, the system can lockdown the Security status bits for the lockable SPIs that are configured as Secure, see Configuration lockdown.
Secure registers, only implemented if the GIC implements the Security Extensions. If the GIC does not implement the Security Extensions the ICDISR addresses are RAZ/WI.
The number of implemented ICDISRs is (ICDICTR.ITLinesNumber + 1), see Interrupt Controller Type Register (ICDICTR). The implemented ICDISRs number upwards from ICDISR0.
In a multiprocessor implementation, ICDISR0 is banked for each connected processor, see Register banking. This register holds the security status bits for interrupts 0-31.
See the register summary in Table 4.1, and ICDISR0 reset value.
Figure 4.4 shows the ICDISR bit assignments.
Table 4.7 shows the ICDISR bit assignments.
Table 4.7. ICDISR bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:0] | Security status bits | For each bit:
|
On start-up or reset, each interrupt with ID32 or higher resets as Secure and therefore all SPIs are Secure unless the system reprograms the appropriate ICDISR bit. See ICDISR0 reset value for information about the reset security configuration of interrupts with IDs 0-31.
ARM recommends that you statically allocate each implemented interrupt as either Secure or Non-secure. To change the security status of an interrupt you must ensure that all the status information for that interrupt is drained before you update the appropriate interrupt Security status bit.
For interrupt ID N, when DIV and MOD are the integer division and modulo operations:
the corresponding ICDISR number, M, is given by M = N DIV 32
the offset of the required ICDISR is (0x080 +
(4*M))
the bit number of the required Security status bit in this register is N MOD 32.
Normally, the reset value of all ICDISRs is zero, so that all interrupts are Secure unless reprogrammed as Non-secure by Secure accesses to the appropriate ICDISRs.
A multiprocessor implementation that supports the Security Extensions might include one or more Non-secure processors, meaning processors that cannot make Secure accesses to the GIC. In this situation only, a GIC can implement a Secure implementation defined mechanism that resets to 1 the ICDISR0 bits for the SGIs and PPIs of any Non-secure processor. This mechanism must apply only to:
a banked ICDISR0 that corresponds to a Non-secure processor
bits in that banked ICDISR0 that correspond to implemented interrupts.
| Copyright © 2008 ARM Limited. All rights reserved. | ARM IHI 0048A |
| Non-Confidential | |
| PDF version | |
| Home > Programmers Model > Distributor register descriptions > Interrupt Security Registers (ICDISRn) |