ARM® Generic Interrupt Controller Architecture Specification: 4.3.7. Interrupt Set-Pending Registers (ICDISPRn)

4.3.7. Interrupt Set-Pending Registers (ICDISPRn)

The ICDISPR characteristics are:

Purpose

The ICDISPRs provide a Set-pending bit for each interrupt supported by the GIC. Writing 1 to a Set-pending bit sets the status of the corresponding peripheral interrupt to pending. Reading a bit identifies whether the interrupt is pending.

Usage constraints

A register bit corresponding to an unimplemented interrupt is RAZ/WI.

If the GIC implements the Security Extensions:

a register bit that corresponds to a Secure interrupt is RAZ/WI to Non-secure accesses
if the GIC implements configuration lockdown, the system can lock down the Set-pending bits for the lockable SPIs that are configured as Secure, see Configuration lockdown.

Set-pending bits for SGIs are read-only and ignore writes.

Configurations

These registers are available in all configurations of the GIC. If the GIC implements the Security Extensions these registers are Common.

The number of implemented ICDISPRs is (ICDICTR.ITLinesNumber + 1), see Interrupt Controller Type Register (ICDICTR). The implemented ICDISPRs number upwards from ICDISPR0.

In a multiprocessor implementation, ICDISPR0 is banked for each connected processor, see Register banking. This register holds the Set-pending bits for interrupts 0-31.

Attributes

See the register summary in Table 4.1.

Figure 4.7 shows the ICDISPR bit assignments.

Figure 4.7. ICDISPR bit assignments

Table 4.10 shows the ICDISPR bit assignments.

Table 4.10. ICDISPR bit assignments

Bits	Name	Function
[31:0]	Set-pending bits	For each bit: Reads 0 The corresponding interrupt is not pending on any processor. 1 For SGIs and PPIs, the corresponding interrupt is pending ^[1] on this processor. For SPIs, the corresponding interrupt is pending ^[1] on at least one processor. Writes For SPIs and PPIs: 0 Has no effect. 1 The effect depends on whether the interrupt is edge-triggered or level-sensitive: Edge-triggered Changes the status of the corresponding interrupt to: pending if it was previously inactive active and pending if it was previously active. Has no effect if the interrupt is already pending ^[1]. Level sensitive If the corresponding interrupt is not pending ^[1], changes the status of the corresponding interrupt to: pending if it was previously inactive active and pending if it was previously active. If the interrupt is already pending ^[1]: because of a write to the ICDISPR, the write has no effect because the corresponding interrupt signal is asserted, the write has no effect on the status of the interrupt, but the interrupt remains pending ^[1] if the interrupt signal is deasserted. For more information see Control of the pending status of level-sensitive interrupts. For SGIs, the write is ignored.
^[1]Pending interrupts include interrupts that are active and pending.

For interrupt ID N, when DIV and MOD are the integer division and modulo operations:

the corresponding ICDISPR number, M, is given by M = N DIV 32
the offset of the required ICDISPR is (0x200 + (4*M))
the bit number of the required Set-pending bit in this register is N MOD 32.

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