ARM® Generic Interrupt Controller Architecture Specification: 4.3.9. Active Bit Registers (ICDABRn)

4.3.9. Active Bit Registers (ICDABRn)

The ICDABR characteristics are:

Purpose

The ICDABRs provide an Active bit for each interupt supported by the GIC. Reading an Active bit identifies whether the corresponding interrupt is active.

Note

The bit reads as one if the status of the interrupt is active or active and pending. Read the ICDSPR or ICDCPR to find the pending status of the interrupt.

Usage constraints

A register bit corresponding to an unimplemented interrupt is RAZ.

If the GIC implements the Security Extensions a register bit that corresponds to a Secure interrupt is RAZ to Non-secure accesses.

Configurations

These registers are available in all configurations of the GIC. If the GIC implements the Security Extensions these registers are Common.

The number of implemented ICDABRs is (ICDICTR.ITLinesNumber + 1), see Interrupt Controller Type Register (ICDICTR). The implemented ICDABRs number upwards from ICDABR0.

In a multiprocessor implementation, ICDABR0 is banked for each connected processor, see Register banking. This register holds the Active bits for interrupts 0-31.

Attributes

See the register summary in Table 4.1.

Figure 4.10 shows the ICDABR bit assignments.

Figure 4.10. ICDABR bit assignments

Table 4.12 shows the ICDABR bit assignments.

Table 4.12. ICDABR bit assignments

Bits	Name	Function
[31:0]	Active bits	For each bit: 0 Corresponding interrupt is not active ^[1]. 1 Corresponding interrupt is active ^[1].
^[1]Active interrupts include interrupts that are active and pending.

For interrupt ID N, when DIV and MOD are the integer division and modulo operations:

the corresponding ICDABR number, M, is given by M = N DIV 32
the offset of the required ICDABR is (0x300 + (4*M))
the bit number of the required Active bit in this register is N MOD 32.

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