ARM® Generic Interrupt Controller Architecture SpecificationArchitecture version 1.0
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ARM® Generic Interrupt Controller Architecture Specification

Architecture version 1.0

Copyright © 2008 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this specification
Intended audience
Using this specification
Conventions
General typographic conventions
Signals
Numbers
Pseudocode descriptions
Further reading
ARM publications
External publications
Feedback
Feedback on this specification
1. Introduction
1.1. About the Generic Interrupt Controller architecture
1.1.1. GIC architecture specification version
1.2. Security Extensions support
1.3. Terminology
1.3.1. Interrupt states
1.3.2. Interrupt types
1.3.3. Models for handling interrupts
1.3.4. Spurious interrupts
1.3.5. Processor security state and Secure and Non-secure GIC accesses
1.3.6. Banking
2. GIC Partitioning
2.1. About GIC partitioning
2.2. The Distributor
2.2.1. Interrupt IDs
2.3. CPU interfaces
3. Interrupt Handling and Prioritization
3.1. About interrupt handling and prioritization
3.1.1. Handling different interrupt types in a multiprocessor system
3.1.2. Identifying the supported interrupts
3.2. General handling of interrupts
3.2.1. Interrupt controls in the GIC
3.2.2. Implications of the 1-N model
3.2.3. Interrupt handling state machine
3.2.4. Special interrupt numbers
3.3. Interrupt prioritization
3.3.1. Preemption
3.3.2. Priority masking
3.3.3. Priority grouping
3.3.4. Interrupt generation
3.4. The effect of the Security Extensions on interrupt handling
3.4.1. Security Extensions support
3.4.2. Special interrupt numbers when the Security Extensions are implemented
3.4.3. Effect of the Security Extensions on interrupt acknowledgement
3.5. The effect of the Security Extensions on interrupt prioritization
3.5.1. Software views of interrupt priority
3.5.2. Control of preemption by Non-secure interrupts
3.5.3. The effect of the Security Extensions on priority masking
3.5.4. The effect of the Security Extensions on priority grouping
3.5.5. Interrupt generation when the GIC implements the Security Extensions
3.5.6. Priority management and the Security Extensions
3.6. Pseudocode details of interrupt handling and prioritization
3.6.1. General helper functions and definitions
3.6.2. Exception generation pseudocode, without the Security Extensions
3.6.3. Exception generation pseudocode, with the Security Extensions
3.6.4. The effect of the Security Extensions on accesses to prioritization registers
4. Programmers Model
4.1. About the programmers model
4.1.1. GIC register short names
4.1.2. Distributor register map
4.1.3. CPU interface register map
4.1.4. GIC register access
4.1.5. Reset behavior
4.2. Effect of the Security Extensions on the programmers model
4.2.1. Non-secure access to register fields for Secure interrupt priorities
4.2.2. Configuration lockdown
4.3. Distributor register descriptions
4.3.1. Distributor Control Register (ICDDCR)
4.3.2. Interrupt Controller Type Register (ICDICTR)
4.3.3. Distributor Implementer Identification Register (ICDIIDR)
4.3.4. Interrupt Security Registers (ICDISRn)
4.3.5. Interrupt Set-Enable Registers (ICDISERn)
4.3.6. Interrupt Clear-Enable Registers (ICDICERn)
4.3.7. Interrupt Set-Pending Registers (ICDISPRn)
4.3.8. Interrupt Clear-Pending Registers (ICDICPRn)
4.3.9. Active Bit Registers (ICDABRn)
4.3.10. Interrupt Priority Registers (ICDIPRn)
4.3.11. Interrupt Processor Targets Registers (ICDIPTRn)
4.3.12. Interrupt Configuration Registers (ICDICFRn)
4.3.13. Software Generated Interrupt Register (ICDSGIR)
4.3.14. Identification registers
4.4. CPU interface register descriptions
4.4.1. CPU Interface Control Register (ICCICR)
4.4.2. Interrupt Priority Mask Register (ICCPMR)
4.4.3. Binary Point Register (ICCBPR)
4.4.4. Interrupt Acknowledge Register (ICCIAR)
4.4.5. End of Interrupt Register (ICCEOIR)
4.4.6. Running Priority Register (ICCRPR)
4.4.7. Aliased Binary Point Register (ICCABPR)
4.4.8. Highest Pending Interrupt Register (ICCHPIR)
4.4.9. CPU Interface Identification Register (ICCIIDR)
A. Pseudocode Index
A.1. Index of pseudocode functions
B. Software Examples for the GIC
B.1. Use of identification registers
B.2. Initialization after reset or power on
B.3. Processor response to an initial interrupt
B.3.1. Effect of the Security Extensions on handling an initial interrupt
B.4. Preemptive processing
B.4.1. CPU interface signalling of interrupts for possible preemption
B.4.2. ARM recommendations for interrupt handling with the Security Extensions
B.5. Generating a software interrupt
B.6. Changing a CPU interface interrupt priority mask
B.7. Changing the priority of an interrupt
B.8. Changing the processor targets of an interrupt
B.9. Disabling a peripheral interrupt
B.10. Changing the security configuration of an interrupt
B.11. Disabling a CPU interface on the GIC
B.12. Message passing between processors
B.13. Example of using the binary point
C. Register Shortform Names
C.1. Register name aliases
C.2. Index of architectural shortform names
Glossary

List of Figures

2.1. GIC logical partitioning into Distributor and CPU interfaces
3.1. Interrupt handling state machine
3.2. Secure view of the priority field for a Secure interrupt
3.3. Non-secure view of the priority field for a Non-secure interrupt
3.4. Secure read of the priority field for a Non-secure interrupt
3.5. Relationship between Secure and Non-secure views of interrupt priority fields
3.6. Software views of the priorities of Non-secure and Secure interrupts
4.1. ICDDCR bit assignments
4.2. ICDICTR Register bit assignments
4.3. ICDIIDR bit assignments
4.4. ICDISR bit assignments
4.5. ICDISER bit assignments
4.6. ICDICER bit assignments
4.7. ICDISPR bit assignments
4.8. ICDICPR bit assignments
4.9. Logic of the pending status of a level-sensitive interrupt
4.10. ICDABR bit assignments
4.11. ICDIPR bit assignments
4.12. ICDIPTR bit assignments
4.13. ICDICFR bit assignments
4.14. ICDSGIR bit assignments
4.15. ICPIDR2 bit assignments
4.16. ARM Peripheral ID fields for a GIC
4.17. ICCICR bit assignments, GIC without Security Extensions and Non-secure ICCICR
4.18. Secure ICCICR bit assignments
4.19. Interrupt signal pass-through
4.20. Secure and Non-secure interrupt signaling, with pass-through
4.21. ICCPMR bit assignments
4.22. ICCBPR bit assignments
4.23. ICCIAR bit assignments
4.24. ICCEOIR bit assignments
4.25. ICCRPR bit assignments
4.26. ICCHPIR bit assignments
4.27. ICCIIDR bit assignments

List of Tables

3.1. Effect of not implementing some LS priority field bits
3.2. Priority grouping by binary point
3.3. Effect of not implementing some LS priority field bits, with Security Extensions
3.4. Priority grouping for Non-secure interrupts
4.1. Distributor register map
4.2. CPU interface register map
4.3. Registers implemented differently when the GIC includes the Security Extensions
4.4. ICDDCR bit assignments
4.5. ICDICTR Register bit assignments
4.6. ICDIIDR bit assignments
4.7. ICDISR bit assignments
4.8. ICDISER bit assignments
4.9. ICDICER bit assignments
4.10. ICDISPR bit assignments
4.11. ICDICPR bit assignments
4.12. ICDABR bit assignments
4.13. ICDIPR bit assignments
4.14. ICDIPTR bit assignments
4.15. Meaning of CPU targets field bit values
4.16. ICDICFR bit assignments
4.17. ICDICFR Int_config[0] encoding in some early GIC implementations
4.18. ICDSGIR bit assignments
4.19. Truth table for sending an SGI to a target processor
4.20. The GIC identification register space
4.21. ICPIDR2 bit assignments
4.22. Identification Registers for a GIC, with ARM implementation values
4.23. Fields in the GIC Peripheral ID, for an ARM implementation
4.24. ICCICR bit assignments, GIC without Security Extensions and Non-secure ICCICR
4.25. Secure ICCICR bit assignments
4.26. Interrupt pass through behavior
4.27. ICCPMR Register bit assignments
4.28. ICCBPR bit assignments
4.29. ICCIAR bit assignments
4.30. Effect of the Security Extensions on ICCIAR reads
4.31. ICCEOIR bit assignments
4.32. Effect of the Security Extensions on ICCEOIR writes
4.33. ICCRPR bit assignments
4.34. ICCHPIR bit assignments
4.35. Effect of the Security Extensions on ICCHPIR reads
4.36. ICCIIDR bit assignments
A.1. Pseudocode functions and procedures
B.1. Preemption example with three interrupts
C.1. Shortform names for the registers in the Distributor
C.2. Shortform names for the registers in the CPU interface
C.3. Index of register shortform names

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

  1. Subject to the provisions of Clauses 2 and 3, ARM hereby grants to you a perpetual, non-exclusive, non-transferable, royalty free, worldwide licence to use and copy the ARM Generic Interrupt Controller (GIC) Architecture Specification (“Specification”) for the purpose of developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products which comply with the Specification and which contain at least one processor core which has either been (i) developed by or for ARM or (ii) developed under licence from ARM.

  2. THE ARM GIC ARCHITECTURE SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE.

  3. No licence, express, implied or otherwise, is granted to you, under the provisions of Clause 1, to use the ARM tradename in connection with the ARM GIC Architecture Specification or any products based thereon. Nothing in Clause 1 shall be construed as authority for you to make any representations on behalf of ARM in respect of the ARM GIC Architecture Specification.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Copyright © 2008 ARM Limited

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Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19.

This document is Non-Confidential. The right to use, copy and disclose this document is subject to the licence set out above.

Unrestricted Access is an ARM internal classification.

Revision History
Revision A23 September 2008First release for version 1.0

Abstract

This is the Architecture Specification for the ARM Generic Interrupt Controller. It is written for users who want to design, implement, or program an ARM GIC. The GIC can be implemented in uniprocessor or multiprocessor systems, and can inclued the ARM Security Extensions.

Copyright © 2008 ARM Limited. All rights reserved.ARM IHI 0048A
Non-ConfidentialUnrestricted Access
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