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| Home > Programmers’ Model > Distributor register descriptions > SGI Set-Pending Registers, GICD_SPENDSGIRn |
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The GICD_SPENDSGIR characteristics are:
The GICD_SPENDSGIRn registers provide a set-pending bit for each supported SGI and source processor combination. When a processor writes a 1 to a set-pending bit, the pending state is applied to the corresponding SGI for the corresponding source processor. Writing a 0 has no effect. Reading a bit identifies whether the SGI is pending, from the corresponding source processor, on the reading processor.
These registers are used when preserving and restoring GIC state.
In these registers, and in the GICD_CPENDSGIRn registers, an SGI is identified by the combination of SGI number and source processor.
A register bit corresponding to an unimplemented SGI is RAZ/WI.
These registers are byte-accessible.
If the GIC implements the Security Extensions:
a register bit that corresponds to a Group 0 interrupt is RAZ/WI to Non-secure accesses
if the GIC supports fewer than eight processors, register bits corresponding to the non-implemented processors are RAZ/WI.
In a multiprocessor implementation, the processor accessing the register can change the SGI pending status only on the corresponding interface. Changing the pending status of an SGI for one target processor does not affect the status of that SGI on any other processor.
PPIs and SPIs both use the Interrupt Set-Pending registers, GICD_ISPENDRn.
These registers are present only in GICv2. The register locations are reserved in GICv1.
Four SGI Set-Pending registers are implemented. The registers contain a bit for each of eight possible source processors, for each of the 16 possible SGIs. That is, each register contains eight set-pending bits for each of four SGIs.
In a multiprocessor implementation, the GICD_SPENDSGIRn registers are banked for each connected processor.
See the register summary in Table 4.1.
Figure 4.19 shows the GICD_SPENDSGIRn bit assignments.
Table 4.24 shows the GICD_SPENDSGIR bit assignments.
Table 4.24. GICD_SPENDSGIRn bit assignments
| Bits | Name | Function |
|---|---|---|
| [8y+7:8y], for y=0 to 3 | SGI x Set-pending bits | For each bit:
See text for the relation between the SGI number, x, the GICD_SPENDSGIRn register number, n, and the field number, y. NoteAll accesses relate only to SGIs that target the processor making the access. |
[a] Pending interrupts include interrupts that are active and pending. | ||
For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and modulo operations:
the corresponding GICD_SPENDSGIR register number, n, is given by n = x DIV 4
the offset of the required GICD_SPENDSGIR is (0xF20 +
(4*n))
the SGI Set-pending field offset, y, is given by y = x MOD 4
the required bit in the SGI x Set-pending field is bit C.
| Copyright © 2008, 2011 ARM Limited. All rights reserved. | ARM IHI 0048B |
| Non-Confidential | ID061411 |
| PDF version | |
| Home > Programmers’ Model > Distributor register descriptions > SGI Set-Pending Registers, GICD_SPENDSGIRn |