ARM Generic Interrupt Controller Architecture Specification

Architecture version 2.0

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ARM^® Generic Interrupt Controller Architecture Specification

Architecture version 2.0

Copyright © 2008, 2011 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

About this specification

Intended audience

Using this specification

Conventions

General typographic conventions
Signals
Numbers
Pseudocode descriptions

Additional reading

ARM publications
Other publications

Feedback on this specification

1. Introduction

1.1. About the Generic Interrupt Controller architecture

1.1.1. GIC architecture specification version
1.1.2. Changes in version 2.0 of the Specification

1.2. Security Extensions support

1.3. Virtualization support

1.4. Terminology

1.4.1. Interrupt states
1.4.2. Interrupt types
1.4.3. Models for handling interrupts
1.4.4. Spurious interrupts
1.4.5. Processor security state and Secure and Non-secure GIC accesses
1.4.6. Banking

2. GIC Partitioning

2.1. About GIC partitioning

2.2. The Distributor

2.2.1. Interrupt IDs

2.3. CPU interfaces

2.3.1. Interrupt signal bypass, and GICv2 bypass disable
2.3.2. Power management, GIC v2

3. Interrupt Handling and Prioritization

3.1. About interrupt handling and prioritization

3.1.1. Handling different interrupt types in a multiprocessor system
3.1.2. Identifying the supported interrupts

3.2. General handling of interrupts

3.2.1. Priority drop and interrupt deactivation
3.2.2. Interrupt controls in the GIC
3.2.3. Implications of the 1-N model
3.2.4. Interrupt handling state machine
3.2.5. Special interrupt numbers

3.3. Interrupt prioritization

3.3.1. Preemption
3.3.2. Priority masking
3.3.3. Priority grouping
3.3.4. Interrupt generation

3.4. The effect of interrupt grouping on interrupt handling

3.4.1. GIC interrupt grouping support
3.4.2. Special interrupt numbers when a GIC supports interrupt grouping
3.4.3. The effect of interrupt grouping on interrupt acknowledgement
3.4.4. GIC power on or reset configuration

3.5. Interrupt grouping and interrupt prioritization

3.5.1. Software views of interrupt priority in a GIC that includes the Security Extensions
3.5.2. Control of preemption by Group 1 interrupts
3.5.3. The effect of interrupt grouping on priority grouping
3.5.4. Interrupt generation when the GIC supports interrupt grouping

3.6. Additional features of the GIC Security Extensions

3.6.1. Access from processors not implementing the ARM Security Extensions
3.6.2. The effect of the GIC Security Extensions on priority masking
3.6.3. Priority management and the GIC Security Extensions

3.7. Pseudocode details of interrupt handling and prioritization

3.7.1. General helper functions and definitions
3.7.2. Exception generation pseudocode
3.7.3. The effect of the GIC Security Extensions on accesses to prioritization registers

3.8. The effect of the Virtualization Extensions on interrupt handling

3.9. Example GIC usage models

3.9.1. Using IRQs and FIQs to provide Non-secure and Secure interrupts
3.9.2. Supporting IRQs and FIQs when not using the processor Security Extensions
3.9.3. Supporting IRQs and FIQs in a virtualized processor environment

4. Programmers’ Model

4.1. About the programmers’ model

4.1.1. GIC register names
4.1.2. Distributor register map
4.1.3. CPU interface register map
4.1.4. GIC register access
4.1.5. Enabling and disabling the Distributor and CPU interfaces

4.2. Effect of the GIC Security Extensions on the programmers’ model

4.2.1. Non-secure access to register fields for Group 0 interrupt priorities
4.2.2. Configuration lockdown
4.2.3. Effect of the Virtualization Extensions on the programmers’ model

4.3. Distributor register descriptions

4.3.1. Distributor Control Register, GICD_CTLR
4.3.2. Interrupt Controller Type Register, GICD_TYPER
4.3.3. Distributor Implementer Identification Register, GICD_IIDR
4.3.4. Interrupt Group Registers, GICD_IGROUPRn
4.3.5. Interrupt Set-Enable Registers, GICD_ISENABLERn
4.3.6. Interrupt Clear-Enable Registers, GICD_ICENABLERn
4.3.7. Interrupt Set-Pending Registers, GICD_ISPENDRn
4.3.8. Interrupt Clear-Pending Registers, GICD_ICPENDRn
4.3.9. Interrupt Set-Active Registers, GICD_ISACTIVERn
4.3.10. Interrupt Clear-Active Registers, GICD_ICACTIVERn
4.3.11. Interrupt Priority Registers, GICD_IPRIORITYRn
4.3.12. Interrupt Processor Targets Registers, GICD_ITARGETSRn
4.3.13. Interrupt Configuration Registers, GICD_ICFGRn
4.3.14. Non-secure Access Control Registers, GICD_NSACRn
4.3.15. Software Generated Interrupt Register, GICD_SGIR
4.3.16. SGI Clear-Pending Registers, GICD_CPENDSGIRn
4.3.17. SGI Set-Pending Registers, GICD_SPENDSGIRn
4.3.18. Identification registers

4.4. CPU interface register descriptions

4.4.1. CPU Interface Control Register, GICC_CTLR
4.4.2. Interrupt Priority Mask Register, GICC_PMR
4.4.3. Binary Point Register, GICC_BPR
4.4.4. Interrupt Acknowledge Register, GICC_IAR
4.4.5. End of Interrupt Register, GICC_EOIR
4.4.6. Running Priority Register, GICC_RPR
4.4.7. Highest Priority Pending Interrupt Register, GICC_HPPIR
4.4.8. Aliased Binary Point Register, GICC_ABPR
4.4.9. Aliased Interrupt Acknowledge Register, GICC_AIAR
4.4.10. Aliased End of Interrupt Register, GICC_AEOIR
4.4.11. Aliased Highest Priority Pending Interrupt Register, GICC_AHPPIR
4.4.12. Active Priorities Registers, GICC_APRn
4.4.13. Non-secure Active Priorities Registers, GICC_NSAPRn
4.4.14. CPU Interface Identification Register, GICC_IIDR
4.4.15. Deactivate Interrupt Register, GICC_DIR

4.5. Preserving and restoring GIC state

5. GIC Support for Virtualization

5.1. About implementing a GIC in a system with processor virtualization

5.2. Managing the GIC virtual CPU interface

5.2.1. List registers and virtual interrupt handling
5.2.2. Completion of virtualized physical interrupts
5.2.3. Acknowledgement and completion of virtual interrupts
5.2.4. GIC virtual interface control interface requirements
5.2.5. Maintenance interrupts
5.2.6. Software-generated interrupts
5.2.7. GIC Virtualization Extensions register mapping

5.3. GIC virtual interface control registers

5.3.1. Hypervisor Control Register, GICH_HCR
5.3.2. VGIC Type Register, GICH_VTR
5.3.3. Virtual Machine Control Register, GICH_VMCR
5.3.4. Maintenance Interrupt Status Register, GICH_MISR
5.3.5. End of Interrupt Status Registers, GICH_EISR0 and GICH_EISR1
5.3.6. Empty List Register Status Registers, GICH_ELRSR0 and GICH_ELRSR1
5.3.7. Active Priorities Register, GICH_APR
5.3.8. List Registers, GICH_LRn

5.4. The virtual CPU interface

5.4.1. Enabling and disabling virtual interrupts

5.5. GIC virtual CPU interface registers

5.5.1. Virtual Machine Control Register, GICV_CTLR
5.5.2. VM Priority Mask Register, GICV_PMR
5.5.3. VM Binary Point Register, GICV_BPR
5.5.4. VM Interrupt Acknowledge Register, GICV_IAR
5.5.5. VM End of Interrupt Register, GICV_EOIR
5.5.6. VM Running Priority Register, GICV_RPR
5.5.7. VM Highest Priority Pending Interrupt Register, GICV_HPPIR
5.5.8. VM Aliased Binary Point Register, GICV_ABPR
5.5.9. VM Aliased Interrupt Acknowledge Register, GICV_AIAR
5.5.10. VM Aliased End of Interrupt Register, GICV_AEOIR
5.5.11. VM Aliased Highest Priority Pending Interrupt Register, GICV_AHPPIR
5.5.12. VM Active Priorities Registers, GICV_APRn
5.5.13. VM CPU Interface Identification Register, GICV_IIDR
5.5.14. VM Deactivate Interrupt Register, GICV_DIR

A. Pseudocode Index

A.1. Index of pseudocode functions

B. Register Names

B.1. Alternative register names
B.2. Register name aliases
B.3. Index of architectural names

C. Revisions

List of Figures

2.1. GIC logical partitioning
2.2. Interrupt signal bypass, GICv1 without Security Extensions
2.3. GICv1 Group 0 and Group 1 interrupt signaling, with interrupt signal bypass
2.4. GICv2 interrupt bypass logic, with bypass disable
3.1. Interrupt handling state machine
3.2. Reset configuration of a GIC that includes the FIQ exception request
3.3. Secure view of the priority field for any interrupt
3.4. Non-secure view of the priority field for a Group 1 interrupt
3.5. Secure read of the priority field for a Group 1 interrupt
3.6. Relationship between Secure and Non-secure views of interrupt priority fields
3.7. Software views of the priorities of Group 1 and Group 0 interrupts
3.8. Generic GIC usage model
3.9. Using the GIC to route Secure and Non-secure interrupts
3.10. Using interrupt grouping to route IRQs and FIQs
3.11. Using the GIC in a virtualized system
4.1. GICD_CTLR bit assignments, GICv1 without Security Extensions or Non-secure
4.2. GICD_CTLR bit assignments, GICv2, and GICv1 Secure copy
4.3. GICD_TYPER bit assignments
4.4. GICD_IIDR bit assignments
4.5. GICD_IGROUPR bit assignments
4.6. GICD_ISENABLER bit assignments
4.7. GICD_ICENABLER bit assignments
4.8. GICD_ISPENDR bit assignments
4.9. GICD_ICPENDR bit assignments
4.10. Logic of the pending status of a level-sensitive interrupt
4.11. GICD_ISACTIVER bit assignments
4.12. GICD_ICACTIVER bit assignments
4.13. GICD_IPRIORITYR bit assignments
4.14. GICD_ITARGETSR bit assignments
4.15. GICD_ICFGR bit assignments
4.16. GICD_NSACR bit assignments
4.17. GICD_SGIR bit assignments
4.18. GICD_CPENDSGIR bit assignments
4.19. GICD_SPENDSGIR bit assignments
4.20. ICPIDR2 bit assignments
4.21. ARM Peripheral ID fields for a GIC
4.22. GICC_CTLR bit assignments, GICv1 without Security Extensions or Non-secure
4.23. GICC_CTLR bit assignments, GICv2 with Security Extensions, Non-secure copy
4.24. GICC_CTLR bit assignments, GICv2 without Security Extensions or Secure
4.25. GICC_PMR bit assignments
4.26. GICC_BPR bit assignments
4.27. GICC_IAR bit assignments
4.28. GICC_EOIR bit assignments
4.29. GICC_RPR bit assignments
4.30. GICC_HPPIR bit assignments
4.31. GICC_ABPR bit assignments
4.32. GICC_AIAR bit assignments
4.33. GICC_AEOIR bit assignments
4.34. GICC_AHPPIR bit assignments
4.35. GICC_IIDR bit assignments
4.36. GICC_DIR bit assignments
5.1. Implementing the GIC with an ARM processor that supports virtualization
5.2. GIC virtual interface control register mappings
5.3. GICH_HCR bit assignments
5.4. GICH_VTR bit assignments
5.5. GICH_VMCR bit assignments
5.6. GICH_MISR bit assignments
5.7. GICH_EISR0 bit assignments
5.8. GICH_ELRSR0 bit assignments
5.9. GICH_APR bit assignments
5.10. GICH_LR bit assignments
5.11. GICV_CTLR bit assignments
5.12. GICV_PMR bit assignments
5.13. GICV_BPR bit assignments
5.14. GICV_IAR bit assignments
5.15. GICV_EOIR bit assignments
5.16. GICV_RPR bit assignments
5.17. GICV_HPPIR bit assignments
5.18. GICV_ABPR bit assignments
5.19. GICV_AIAR bit assignments
5.20. GICV_AEOIR bit assignments
5.21. GICV_AHPPIR bit assignments
5.22. GICV_IIDR bit assignments
5.23. GICV_DIR bit assignments

List of Tables

2.1. Interrupt signal bypass behavior, GICv1 with Security Extensions
2.2. IRQ request behavior, GICv2
2.3. FIQ request behavior, GICv2
3.1. Effect of not implementing some priority field bits
3.2. Priority grouping by binary point
3.3. Binary point register used to calculate priority grouping
3.4. CPU interface control of Group 0 and Group 1 interrupts, GICv2
3.5. CPU interface Non-secure control of Group 1 interrupts
3.6. Effect of not implementing some priority field bits, with GIC Security Extensions
3.7. Priority grouping for Group 1 interrupts when GICC_CTLR.CBPR==0
4.1. Distributor register map
4.2. CPU interface register map
4.3. Registers implemented differently when the GIC includes the GIC Security Extensions
4.4. GICD_CTLR bit assignments, GICv1 without Security Extensions or Non-secure
4.5. GICD_CTLR bit assignments, GICv2, and GICv1 Secure copy
4.6. GICD_TYPER bit assignments
4.7. GICD_IIDR bit assignments
4.8. GICD_IGROUPR bit assignments
4.9. GICD_ISENABLER bit assignments
4.10. GICD_ICENABLER bit assignments
4.11. GICD_ISPENDR bit assignments
4.12. GICD_ICPENDR bit assignments
4.13. GICD_ISACTIVER bit assignments
4.14. GICD_ICACTIVER bit assignments
4.15. GICD_IPRIORITYR bit assignments
4.16. GICD_ITARGETSR bit assignments
4.17. Meaning of CPU targets field bit values
4.18. GICD_ICFGR bit assignments
4.19. GICD_ICFGR Int_config[0] encoding in some early GIC implementations
4.20. GICD_NSACR bit assignments
4.21. GICD_SGIR bit assignments
4.22. Truth table for sending an SGI to a target processor
4.23. GICD_CPENDSGIRn bit assignments
4.24. GICD_SPENDSGIRn bit assignments
4.25. The GIC identification register space
4.26. ICPIDR2 bit assignments
4.27. Identification Registers for a GIC, with ARM implementation values
4.28. Fields in the GIC Peripheral ID, for an ARM implementation
4.29. GICC_CTLR bit assignments, GIC1 without Security Extensions or Non-secure
4.30. GICC_CTLR bit assignments, GIC2 with Security Extensions, Non-secure copy
4.31. GICC_CTLR bit assignments, GICv2 without Security Extensions or Secure
4.32. GICC_PMR Register bit assignments
4.33. GICC_BPR bit assignments
4.34. GICC_IAR bit assignments
4.35. Effect of interrupt grouping and the Security Extensions on reads of GICC_IAR
4.36. GICC_EOIR bit assignments
4.37. Effect of the Security Extensions on writes to GICC_EOIR
4.38. Priority drop effect of GICC_EOIR writes
4.39. Deactivate interrupt effect of GICC_EOIR writes
4.40. GICC_RPR bit assignments
4.41. GICC_HPPIR bit assignments
4.42. Effect of the Security Extensions on GICC_HPPIR reads
4.43. GICC_ABPR bit assignments
4.44. GICC_AIAR bit assignments
4.45. GICC_AEOIR bit assignments
4.46. GICC_AHPPIR bit assignments
4.47. Active Priorities register implementation
4.48. GICC_IIDR bit assignments
4.49. GICC_DIR bit assignments
4.50. Behavior of GICC_DIR writes
5.1. GIC virtual interface control register map
5.2. GICH_HCR bit assignments
5.3. GICH_VTR bit assignments
5.4. GICH_VMCR bit assignments
5.5. GICH_MISR bit assignments
5.6. GICH_EISR0 bit assignments
5.7. GICH_ELRSR0 bit assignments
5.8. GICH_APR bit assignments
5.9. GICH_LR bit assignments
5.10. GIC virtual CPU interface register map
5.11. GICV_CTLR bit assignments
5.12. Effect of reads of GICV_IAR
5.13. GICV_EOIR operation
5.14. GICV_HPPIR operation
5.15. GICV_AIAR operation
5.16. GICV_AEOIR operation
5.17. GICV_AHPPIR operation
A.1. Pseudocode functions and procedures
B.1. Replacement names for the registers in the Distributor
B.2. Replacement names for the registers in the CPU interface
B.3. Alias names for the registers in the Distributor
B.4. Alias names for the registers in the CPU interface
B.5. Index of GIC register names
C.1. Differences between issue A and issue B

Proprietary Notice

Words and logos marked with ^® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

Subject to the provisions of Clauses 2 and 3, ARM hereby grants to you a perpetual, non-exclusive, non-transferable, royalty free, worldwide licence to use and copy the ARM Generic Interrupt Controller (GIC) Architecture Specification (“Specification”) for the purpose of developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products which comply with the Specification and which contain at least one processor core which has either been (i) developed by or for ARM or (ii) developed under licence from ARM.
THE ARM GIC ARCHITECTURE SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE.
No licence, express, implied or otherwise, is granted to you, under the provisions of Clause 1, to use the ARM tradename in connection with the ARM GIC Architecture Specification or any products based thereon. Nothing in Clause 1 shall be construed as authority for you to make any representations on behalf of ARM in respect of the ARM GIC Architecture Specification.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Copyright © 2008, 2011 ARM Limited

110 Fulbourn Road Cambridge, England CB1 9NJ

Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19.

This document is Non-Confidential. The right to use, copy and disclose this document is subject to the licence set out above.

Unrestricted Access is an ARM internal classification.

Revision History
Revision A	23 September 2008	First release for version 1.0
Revision B	13 June 2011	First release for version 2.0

Copyright © 2008, 2011 ARM Limited. All rights reserved.	ARM IHI 0048B
Non-Confidential	ID061411
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