System Trace Macrocell Programmers’ Model Architecture Specification Version 1.0: 4.3.1. DMA control registers

4.3.1. DMA control registers

Table 4.10 shows the example DMA control registers, in register order. In the table, access type is described as follows:

RW: Read and write.
RO: Read only.
WO: Write only.

Table 4.10. Example DMA control registers

Register	Name	Type	Description
`0x00`	-	-	Reserved
`0x04`	Transfer Start	WO	See DMA Transfer Start Register, STMDMASTARTR
`0x08`	Transfer Stop	WO	See DMA Transfer Stop Register, STMDMASTOPR
`0x0C`	Transfer Status	RO	See DMA Transfer Status Register, STMDMASTATR
`0x10`	Control	RW	See DMA Control Register, STMDMACTLR
`0x14`-`0xF8`	-	-	Reserved
`0xFC`	ID	RO	See DMA ID Register, STMDMAIDR

DMA Transfer Start Register, STMDMASTARTR

The STMDMASTARTR characteristics are:

Purpose

Starts a DMA transfer:

a write of b1 when the DMA peripheral request interface is idle starts a DMA transfer
a write of b0 has no effect
a write of b1 when the DMA peripheral request interface is active has no effect.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all implementations.

Attributes

See the register summary in Table 4.10.

Figure 4.8 shows the STMDMASTARTR bit assignments.

Figure 4.8. STMDMASTARTR bit assignments

Table 4.11 shows the STMDMASTARTR bit assignments.

Table 4.11. STMDMASTARTR bit assignments

Bits	Name	Description
[31:1]	-	Reserved, UNK/SBZP.
[0]	START	Start a DMA transfer

DMA Transfer Stop Register, STMDMASTOPR

The STMDMASTOPR characteristics are:

Purpose

Stops a DMA transfer:

a write of b1 stops an active DMA transfer
a write of b0 has no effect
a write of b1 when the DMA peripheral request interface is idle has no effect..

Usage constraints

There are no usage constraints.

Configurations

This register is available in all implementations.

Attributes

See the register summary in Table 4.10.

Figure 4.9 shows the STMDMASTOPR bit assignments.

Figure 4.9. STMDMASTOPR bit assignments

Table 4.12 shows the STMDMASTOPR bit assignments.

Table 4.12. STMDMASTOPR bit assignments

Bits	Name	Description
[31:1]	-	Reserved, UNK/SBZP.
[0]	STOP	Stop a DMA transfer

DMA Transfer Status Register, STMDMASTATR

The STMDMASTATR characteristics are:

Purpose: Indicates whether a DMA transfer is in progress.
Usage constraints: There are no usage constraints.
Configurations: This register is available in all implementations.
Attributes: See the register summary in Table 4.10.

Figure 4.10 shows the STMDMASTATR bit assignments.

Figure 4.10. STMDMASTATR bit assignments

Table 4.13 shows the STMDMASTATR bit assignments.

Table 4.13. STMDMASTATR bit assignments

Bits

Name

Description

[31:1]

Reserved, UNK/SBZP.

[0]

STATUS

Status of the DMA peripheral request interface:

b0 = interface is idle

b1 = interface is active.

DMA Control Register, STMDMACTLR

The STMDMACTLR characteristics are:

Purpose: Controls the DMA transfer request mechanism.
Usage constraints: There are no usage constraints.
Configurations: This register is available in all implementations.
Attributes: See the register summary in Table 4.10.

Figure 4.11 shows the STMDMACTLR bit assignments.

Figure 4.11. STMDMACTLR bit assignments

Table 4.14 shows the STMDMACTLR bit assignments.

Table 4.14. STMDMACTLR bit assignments

Bits	Name	Description
[31:4]	-	Reserved, UNK/SBZP.
[3:0]	SENS	Determines the sensitivity of the DMA request to the current buffer level in the STM. A smaller value indicates that the STM waits for a large amount of buffer space to be available before requesting a DMA transfer. Not all bits of this field might be implemented. Lower order bits might not be implemented. To detect the implemented bits, write b1111 to this field and read it back. The bits that return b1 are implemented. If no bits are implemented, there is no control over the sensitivity. Reset value is b0000.

Bits

Name

Description

[31:4]

Reserved, UNK/SBZP.

[3:0]

SENS

Determines the sensitivity of the DMA request to the current buffer level in the STM.

A smaller value indicates that the STM waits for a large amount of buffer space to be available before requesting a DMA transfer.

Not all bits of this field might be implemented. Lower order bits might not be implemented. To detect the implemented bits, write b1111 to this field and read it back. The bits that return b1 are implemented. If no bits are implemented, there is no control over the sensitivity.

Reset value is b0000.

The STMDMACTL.SENS field is a hint to the hardware and does not necessarily correspond to any specific buffer levels. This field is intended to be used to balance the usage of the STM to ensure there is sufficient buffer space and appropriate throughput.

DMA ID Register, STMDMAIDR

This register uses the b0010 encoding of the CLASS field. For more information about this register, see About implementation defined controls and registers.

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