System Trace Macrocell Programmers’ Model Architecture Specification Version 1.0
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System Trace Macrocell Programmers’ Model Architecture Specification Version 1.0

Copyright © 2010 ARM. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the System Trace Macrocell
2. Configuration Registers Programmers’ Model
2.1. About the configuration registers programmers’ model
2.2. Register summary
2.3. Register descriptions
2.3.1. Basic Stimulus Ports, STMSTIMR<n>
2.3.2. Stimulus Port Enable Register, STMSPER
2.3.3. Stimulus Port Trigger Enable Register, STMSPTER
2.3.4. Trace Privilege Register, STMPRIVMASKR
2.3.5. Stimulus Port Select Configuration Register, STMSPSCR
2.3.6. Stimulus Port Master Select Configuration Register, STMSPMSCR
2.3.7. Stimulus Port Override Register, STMSPOVERRIDER
2.3.8. Stimulus Port Master Override Register, STMSPMOVERRIDER
2.3.9. Stimulus Port Trigger Control and Status Register, STMSPTRIGCSR
2.3.10. Trace Control and Status Register, STMTCSR
2.3.11. Timestamp Stimulus Register, STMTSSTIMR
2.3.12. Timestamp Frequency Register, STMTSFREQR
2.3.13. Synchronization Control Register, STMSYNCR
2.3.14. Auxiliary Control Register, STMAUXCR
2.3.15. Features 1 Register, STMFEAT1R
2.3.16. Features 2 Register, STMFEAT2R
2.3.17. Features 3 Register, STMFEAT3R
2.3.18. Integration Mode Control Register, STMITCTRL
2.3.19. Claim Tag Registers
2.3.20. Lock Registers
2.3.21. Authentication Status Register, STMAUTHSTATUS
2.3.22. Device Configuration Register, STMDEVID
2.3.23. Device Type Register, STMDEVTYPE
2.3.24. Peripheral ID Registers, STMPIDR0-7
2.3.25. Component ID Registers, STMCIDR0-3
2.4. Programming the STM
2.4.1. Modifying the STMSPSCR and STMSPMSCR
2.4.2. Modifying the STMSYNCR
2.5. Triggers
2.5.1. Triggers caused by matches using the STMSPTER
2.5.2. Triggers caused by matches using the STMHETER
2.5.3. Triggers caused by writes to TRIG locations in the extended stimulus port
2.6. Authentication control
3. Extended Stimulus Ports
3.1. About extended stimulus ports
3.2. STM transactions
3.2.1. Guaranteed transactions
3.2.2. Invariant timing transactions
3.3. Address decoding
3.4. Grouping stimulus ports
3.5. More than one master
3.6. Data sizes
3.7. Bus endianness
3.8. Implementation options
3.9. Reserved locations
3.10. Timestamping
3.11. Mapping onto STPv2
4. Implementation Defined Controls
4.1. About implementation defined controls and registers
4.2. Standard hardware event tracing
4.2.1. Hardware event control registers
4.2.2. Changing the STM programming
4.2.3. Tracing hardware events
4.3. DMA control
4.3.1. DMA control registers
A. Recommended Implementation
A.1. About recommended implementation
Glossary

List of Figures

1.1. STM inputs and outputs
2.1. STMSTIMR<n> bit assignments on reads
2.2. STMSPER bit assignments
2.3. STMSPTER bit assignments
2.4. STMPRIVMASKR bit assignments
2.5. STMSPSCR bit assignments
2.6. STMSPMSCR bit assignments
2.7. STMSPOVERRIDER bit assignments
2.8. STMSPMOVERRIDER bit assignments
2.9. STMSPTRIGCSR bit assignments
2.10. STMTCSR bit assignments
2.11. STMTSSTIMR bit assignments
2.12. STMTSFREQR bit assignments
2.13. STMSYNCR bit assignments
2.14. STMFEAT1R bit assignments
2.15. STMFEAT2R bit assignments
2.16. STMFEAT3R bit assignments
2.17. STMITCTRL Register bit assignments
2.18. STMCLAIMSET Register bit assignments
2.19. STMCLAIMCLR register bit assignments
2.20. STMLAR bit assignments
2.21. STMLSR bit assignments
2.22. STMDEVID Register bit assignments
2.23. STMDEVTYPE register bit assignments
4.1. Implementation Defined Controls Identification Register bit assignments
4.2. STMHEER bit assignments
4.3. STMHETER bit assignments
4.4. STMHEBSR bit assignments
4.5. STMHEMCR bit assignments
4.6. STMHEMASTR bit assignments
4.7. STMHEFEAT1R bit assignments
4.8. STMDMASTARTR bit assignments
4.9. STMDMASTOPR bit assignments
4.10. STMDMASTATR bit assignments
4.11. STMDMACTLR bit assignments

List of Tables

2.1. STM configuration register summary
2.2. STMSTIMR<n> bit assignments on reads
2.3. STMSPER bit assignments
2.4. STMSPTER bit assignments
2.5. STMPRIVMASKR bit assignments
2.6. STMSPSCR bit assignments
2.7. Using PORTCTL
2.8. STMSPMSCR bit assignments
2.9. Using MASTCTL
2.10. STMSPOVERRIDER bit assignments
2.11. Using OVERCTL
2.12. STMSPMOVERRIDER bit assignments
2.13. Using MASTCTL
2.14. STMSPTRIGCSR bit assignments
2.15. STMTCSR bit assignments
2.16. STMTSSTIMR bit assignments
2.17. STMTSFREQR bit assignments
2.18. STMSYNCR bit assignments
2.19. STMAUXCR bit assignments
2.20. STMFEAT1R bit assignments
2.21. STMFEAT2R bit assignments
2.22. STMFEAT3R bit assignments
2.23. STMITCTRL Register bit assignments
2.24. STMCLAIMSET Register bit assignments
2.25. STMCLAIMCLR Register bit assignments
2.26. STMLAR bit assignments
2.27. STMLSR bit assignments
2.28. STMDEVID Register bit assignments
2.29. STMDEVTYPE Register bit assignments
2.30. STMCIDR0-3 values
2.31. Trigger generation summary
2.32. Authentication control with guaranteed override selected
3.1. Address map for a single stimulus port
3.2. Address bit meanings for data accesses
3.3. Address bit meanings for non-data accesses
3.4. Address map for a group of 16 stimulus ports
3.5. Expected packets based on fundamental data size
3.6. Implementation options
4.1. Implementation Defined Controls Identification Register bit assignments
4.2. Standard hardware event tracing control register summary
4.3. STMHEER bit assignments
4.4. STMHETER bit assignments
4.5. STMHEBSR bit assignments
4.6. STMHEMCR bit assignments
4.7. STMHEMASTR bit assignments
4.8. STMHEFEAT1R bit assignments
4.9. Hardware event tracing
4.10. Example DMA control registers
4.11. STMDMASTARTR bit assignments
4.12. STMDMASTOPR bit assignments
4.13. STMDMASTATR bit assignments
4.14. STMDMACTLR bit assignments
A.1. Recommended configuration
A.2. Hardware event tracing recommended configuration

Proprietary Notice

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith.

1. Subject to the provisions set out below, ARM hereby grants to you a perpetual, non-exclusive, nontransferable, royalty free, worldwide licence to use this ARM System Trace Macrocell Architecture Specification for the purposes of developing; (i) software applications or operating systems which are targeted to run on microprocessor cores distributed under licence from ARM; (ii) tools which are designed to develop software programs which are targeted to run on microprocessor cores distributed under licence from ARM; (iii) integrated circuits which incorporate a microprocessor core manufactured under licence from ARM.

2. Except as expressly licensed in Clause 1 you acquire no right, title or interest in the ARM System Trace Macrocell Architecture Specification, or any Intellectual Property therein. In no event shall the licences granted in Clause 1, be construed as granting you expressly or by implication, estoppel or otherwise, licences to any ARM technology other than the ARM System Trace Macrocell Architecture Specification. The licence grant in Clause 1 expressly excludes any rights for you to use or take into use any ARM patents. No right is granted to you under the provisions of Clause 1 to; (i) use the ARM System Trace Macrocell Architecture Specification for the purposes of developing or having developed microprocessor cores or models thereof which are compatible in whole or part with either or both the instructions or programmers’ models described in this ARM System Trace Macrocell Architecture Specification; or (ii) develop or have developed models of any microprocessor cores designed by or for ARM; or (iii) distribute in whole or in part this ARM System Trace Macrocell Architecture Specification to third parties without the express written permission of ARM; or (iv) translate or have translated this ARM System Trace Macrocell Architecture Specification into any other languages.

3. THE ARM SYSTEM TRACE MACROCELL ARCHITECTURE SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE.

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Copyright © 2010 ARM Limited

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Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A23 April 2010First release for v1.0
Copyright © 2010 ARM. All rights reserved.ARM IHI 0054A
Non-ConfidentialID090710
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