RealView Assembler User's Guide

Keil™, An ARM® Company

Version 4.0


Table of Contents

Preface
About this book
Intended audience
Using this book
Typographical conventions
Further reading
Feedback
Feedback on RealView Compilation Tools
Feedback on this book
1. Introduction
1.1. About the RealView Compilation Tools assemblers
1.1.1. ARM assembly language
2. Writing ARM Assembly Language
2.1. Introduction
2.2. Overview of the ARM architecture
2.2.1. Architecture versions
2.2.2. ARM, Thumb, Thumb-2, and Thumb-2EE instruction sets
2.2.3. ARM, Thumb, and ThumbEE state
2.2.4. Processor mode
2.2.5. Registers
2.2.6. Instruction set overview
2.2.7. Instruction capabilities
2.3. Structure of assembly language modules
2.3.1. Layout of assembly language source files
2.3.2. An example ARM assembly language module
2.3.3. Calling subroutines
2.4. Conditional execution
2.4.1. The ALU status flags
2.4.2. Conditional execution
2.4.3. Using conditional execution
2.4.4. Example of the use of conditional execution
2.4.5. The Q flag
2.5. Loading constants into registers
2.5.1. Direct loading with MOV and MVN
2.5.2. Loading with MOV32
2.5.3. Loading with LDR Rd, =const
2.6. Loading addresses into registers
2.6.1. Direct loading with ADR and ADRL
2.6.2. Loading addresses with LDR Rd, =label
2.7. Load and store multiple register instructions
2.7.1. Load and store multiple instructions available in ARM and Thumb
2.7.2. Implementing stacks with LDM and STM
2.7.3. Block copy with LDM and STM
2.8. Using macros
2.8.1. Test-and-branch macro example
2.8.2. Unsigned integer division macro example
2.9. Using frame directives
2.10. Assembly language changes
3. Assembler Reference
3.1. Command syntax
3.1.1. Obtaining a list of available options
3.1.2. Specifying command-line options with an environment variable
3.1.3. AAPCS
3.1.4. Floating-point model
3.1.5. CPU names
3.1.6. FPU names
3.1.7. Memory access attributes
3.1.8. Pre-executing a SET directive
3.1.9. Splitting long LDMs and STMs
3.1.10. Listing output to a file
3.1.11. Controlling the output of diagnostic messages
3.1.12. Controlling exception table generation
3.2. Format of source lines
3.3. Predefined register and coprocessor names
3.3.1. Predeclared register names
3.3.2. Predeclared extension register names
3.3.3. Predeclared coprocessor names
3.4. Built-in variables and constants
3.4.1. Detecting versions of armasm
3.5. Symbols
3.5.1. Symbol naming rules
3.5.2. Variables
3.5.3. Numeric constants
3.5.4. Assembly time substitution of variables
3.5.5. Labels
3.5.6. Local labels
3.6. Expressions, literals, and operators
3.6.1. String expressions
3.6.2. String literals
3.6.3. Numeric expressions
3.6.4. Numeric literals
3.6.5. Floating-point literals
3.6.6. Register-relative and program-relative expressions
3.6.7. Logical expressions
3.6.8. Logical literals
3.6.9. Operator precedence
3.6.10. Unary operators
3.6.11. Binary operators
3.7. Diagnostic messages
3.7.1. Interlocks
3.7.2. IT block generation
3.7.3. Thumb branch target alignment
3.8. Using the C preprocessor
4. ARM and Thumb Instructions
4.1. Instruction summary
4.2. Memory access instructions
4.2.1. Address alignment
4.2.2. LDR and STR (immediate offset)
4.2.3. LDR and STR (register offset)
4.2.4. LDR and STR (User mode)
4.2.5. LDR (pc-relative)
4.2.6. ADR
4.2.7. PLD, PLDW, and PLI
4.2.8. LDM and STM
4.2.9. PUSH and POP
4.2.10. RFE
4.2.11. SRS
4.2.12. LDREX and STREX
4.2.13. CLREX
4.2.14. SWP and SWPB
4.3. General data processing instructions
4.3.1. Flexible second operand
4.3.2. ADD, SUB, RSB, ADC, SBC, and RSC
4.3.3. SUBS pc, lr
4.3.4. AND, ORR, EOR, BIC, and ORN
4.3.5. CLZ
4.3.6. CMP and CMN
4.3.7. MOV and MVN
4.3.8. MOVT
4.3.9. TST and TEQ
4.3.10. SEL
4.3.11. REV, REV16, REVSH, and RBIT
4.3.12. ASR, LSL, LSR, ROR, and RRX
4.3.13. SDIV and UDIV
4.4. Multiply instructions
4.4.1. MUL, MLA, and MLS
4.4.2. UMULL, UMLAL, SMULL, and SMLAL
4.4.3. SMULxy and SMLAxy
4.4.4. SMULWy and SMLAWy
4.4.5. SMLALxy
4.4.6. SMUAD{X} and SMUSD{X}
4.4.7. SMMUL, SMMLA, and SMMLS
4.4.8. SMLAD and SMLSD
4.4.9. SMLALD and SMLSLD
4.4.10. UMAAL
4.5. Saturating instructions
4.5.1. Saturating arithmetic
4.5.2. QADD, QSUB, QDADD, and QDSUB
4.5.3. SSAT and USAT
4.6. Parallel instructions
4.6.1. Parallel add and subtract
4.6.2. USAD8 and USADA8
4.6.3. SSAT16 and USAT16
4.7. Packing and unpacking instructions
4.7.1. BFC and BFI
4.7.2. SBFX and UBFX
4.7.3. SXT, SXTA, UXT, and UXTA
4.7.4. PKHBT and PKHTB
4.8. Branch and control instructions
4.8.1. B, BL, BX, BLX, and BXJ
4.8.2. IT
4.8.3. CBZ and CBNZ
4.8.4. TBB and TBH
4.9. Coprocessor instructions
4.9.1. CDP and CDP2
4.9.2. MCR, MCR2, MCRR, and MCRR2
4.9.3. MRC, MRC2, MRRC and MRRC2
4.9.4. LDC, LDC2, STC, and STC2
4.10. Miscellaneous instructions
4.10.1. BKPT
4.10.2. SVC
4.10.3. MRS
4.10.4. MSR
4.10.5. CPS
4.10.6. SMC
4.10.7. SETEND
4.10.8. NOP, SEV, WFE, WFI, and YIELD
4.10.9. DBG, DMB, DSB, and ISB
4.11. Instruction width selection in Thumb
4.11.1. Instruction width specifiers, .W and .N
4.11.2. Different behavior for some instructions
4.11.3. Diagnostic warning
4.12. ThumbEE instructions
4.12.1. ENTERX and LEAVEX
4.12.2. CHKA
4.12.3. HB, HBL, HBLP, and HBP
4.13. Pseudo-instructions
4.13.1. ADRL pseudo-instruction
4.13.2. MOV32 pseudo-instruction
4.13.3. LDR pseudo-instruction
4.13.4. UND pseudo-instruction
5. Directives Reference
5.1. Alphabetical list of directives
5.2. Symbol definition directives
5.2.1. GBLA, GBLL, and GBLS
5.2.2. LCLA, LCLL, and LCLS
5.2.3. SETA, SETL, and SETS
5.2.4. RELOC
5.2.5. RN
5.2.6. RLIST
5.2.7. CN
5.2.8. CP
5.3. Data definition directives
5.3.1. LTORG
5.3.2. MAP
5.3.3. FIELD
5.3.4. SPACE or FILL
5.3.5. DCB
5.3.6. DCD and DCDU
5.3.7. DCDO
5.3.8. DCFD and DCFDU
5.3.9. DCFS and DCFSU
5.3.10. DCI
5.3.11. DCQ and DCQU
5.3.12. DCW and DCWU
5.3.13. COMMON
5.3.14. DATA
5.4. Assembly control directives
5.4.1. Nesting directives
5.4.2. MACRO and MEND
5.4.3. MEXIT
5.4.4. IF, ELSE, ENDIF, and ELIF
5.4.5. WHILE and WEND
5.5. Frame directives
5.5.1. FRAME ADDRESS
5.5.2. FRAME POP
5.5.3. FRAME PUSH
5.5.4. FRAME REGISTER
5.5.5. FRAME RESTORE
5.5.6. FRAME RETURN ADDRESS
5.5.7. FRAME SAVE
5.5.8. FRAME STATE REMEMBER
5.5.9. FRAME STATE RESTORE
5.5.10. FRAME UNWIND ON
5.5.11. FRAME UNWIND OFF
5.5.12. FUNCTION or PROC
5.5.13. ENDFUNC or ENDP
5.6. Reporting directives
5.6.1. ASSERT
5.6.2. INFO
5.6.3. OPT
5.6.4. TTL and SUBT
5.7. Instruction set and syntax selection directives
5.7.1. ARM, THUMB, THUMBX, CODE16 and CODE32
5.8. Miscellaneous directives
5.8.1. ALIGN
5.8.2. AREA
5.8.3. ATTR
5.8.4. END
5.8.5. ENTRY
5.8.6. EQU
5.8.7. EXPORT or GLOBAL
5.8.8. EXPORTAS
5.8.9. GET or INCLUDE
5.8.10. IMPORT and EXTERN
5.8.11. INCBIN
5.8.12. KEEP
5.8.13. NOFP
5.8.14. REQUIRE
5.8.15. REQUIRE8 and PRESERVE8
5.8.16. ROUT

List of Figures

4.1. ROR
4.2. RRX

List of Tables

2.1. ARM processor modes
2.2. Condition code suffixes
2.3. Conditional branches only
2.4. All instructions conditional
2.5. ARM state immediate constants (8-bit)
2.6. ARM state immediate constants in MOV instructions
2.7. Thumb-2 immediate constants
2.8. Thumb-2 immediate constants in MOV instructions
2.9. Stack-oriented suffixes and equivalent addressing mode suffixes
2.10. Suffixes for load and store multiple instructions
2.11. Changes from earlier ARM assembly language
2.12. Relaxation of requirements
2.13. Differences between pre-UAL Thumb syntax and UAL syntax
3.1. Compatible processor or architecture combinations
3.2. Severity of diagnostic messages
3.3. Built-in variables
3.4. Built-in Boolean constants
3.5. Operator precedence in armasm
3.6. Operator precedence in C
3.7. Unary operators that return strings
3.8. Unary operators that return numeric or logical values
3.9. Multiplicative operators
3.10. String manipulation operators
3.11. Shift operators
3.12. Addition, subtraction, and logical operators
3.13. Relational operators
3.14. Boolean operators
3.15. Command-line options
3.16. armcc equivalent command-line options
4.1. Location of instructions
4.2. Offsets and architectures, LDR/STR, word, halfword, and byte
4.3. Options and architectures, LDR/STR (register offsets)
4.4. Offsets and architectures, LDR/STR (User mode)
4.5. pc-relative offsets
4.6. pc-relative offsets
4.7. Branch instruction availability and range
4.8. Range and encoding of expr
5.1. Location of directives
5.2. OPT directive settings

Proprietary Notice

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Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A May 2007 Release for RVCT for µVision v3.1
Revision B December 2008 Release for RVCT for µVision v4.0
ARM KUI 0100A
Non-Confidential