ARM11 processors

ARM documentation set for the ARM11 family of processors, including ARM1136JF-S and ARM1126J-S, ARM1156T2-S, ARM1156T2F-S, ARM1176JZF, ARM1176JZ-S, ARM1176JZF-S, and ARM11 MPCore processors.

The ARM11 family comprises four series of processors that implement the ARM architecture v6 with extensions including a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.

  • The ARM1136J-S and ARM1136JF-S processors feature ARM Jazelle technology. They implement a Virtual Memory System Architecture and have AMBA 2 AHB interfaces. They support the ARM instruction set and the original Thumb instruction set. The ARM1136JF-S processor has a floating point coprocessor.
  • The ARM1156T2-S and ARM1156T2F-S processors feature optional Memory Protection Units (MPUs) for instruction and data memory, optional parity protection for caches and tightly coupled memories, and have AMBA 3 AXI interfaces. They support the ARM and Thumb instruction sets, with the Thumb-2 extensions. The ARM1156T2F-S processor has a floating point coprocessor.
  • The ARM1176JZ-S and ARM1176JZF-S processors feature ARM TrustZone technology and ARM Jazelle technology, and support ARM Intelligent Energy Manager (IEM) technology. They implement a Virtual Memory System architecture, and have AMBA 3 AXI interfaces. They support the ARM instruction set and the original Thumb instruction set. The ARM1176JZF-S processor has a floating point coprocessor.
  • The ARM11 MPCore multiprocessor is configured to include 1-4 processors that can be viewed as a single processor. It features ARM Jazelle technology, and supports ARM IEM technology. It implements a Virtual Memory System Architecture with configurable level 1 caches, a vector floating point coprocessor, and programmable interrupt control and distribution, and has AMBA 3 AXI interfaces. It supports the ARM instruction set and the original Thumb instruction set.

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